3645cef1ef
PHI-node part was merged with PR#160909. Extend `isOpLegal` to treat 8/16-bit vector add/sub/and/or/xor as profitable on SDWA targets (stores and intrinsics remain profitable). This repacks loop-carried values to i32 across BBs and restores SDWA lowering instead of scattered lshr/lshl/or sequences. Testing: - Local: `check-llvm-codegen-amdgpu` is green (4314/4320 passed, 6 XFAIL). - Additional: validated in AMD internal CI
64 lines
2.1 KiB
LLVM
64 lines
2.1 KiB
LLVM
; REQUIRES: amdgpu-registered-target
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; RUN: opt -S -passes=amdgpu-late-codegenprepare \
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; RUN: -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s | FileCheck %s
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; Purpose:
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; - Input has a loop-carried PHI of type <4 x i8> and byte-wise adds in the
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; loop header (same basic block as the PHI).
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; - After amdgpu-late-codegenprepare, the PHI must be coerced to i32 across
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; the backedge, and a single dominating "bitcast i32 -> <4 x i8>" must be
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; placed in the header (enabling SDWA-friendly lowering later).
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;
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; What we check:
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; - PHI is i32 (no loop-carried <4 x i8> PHI remains).
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; - A header-local bitcast i32 -> <4 x i8> exists and feeds the vector add.
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; - The loopexit produces a bitcast <4 x i8> -> i32 for the backedge.
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define amdgpu_kernel void @lro_coerce_v4i8_phi(ptr nocapture %p, i32 %n) {
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entry:
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br label %loop
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loop:
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; Loop index
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%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
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; Loop-carried accumulator in vector-of-bytes form (problematic on input).
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%acc = phi <4 x i8> [ zeroinitializer, %entry ], [ %acc.next, %loop ]
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; Make up four i8 values derived from %i to avoid memory noise.
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%i0 = trunc i32 %i to i8
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%i1i = add i32 %i, 1
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%i1 = trunc i32 %i1i to i8
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%i2i = add i32 %i, 2
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%i2 = trunc i32 %i2i to i8
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%i3i = add i32 %i, 3
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%i3 = trunc i32 %i3i to i8
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; Pack them into <4 x i8>.
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%v01 = insertelement <4 x i8> zeroinitializer, i8 %i0, i32 0
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%v02 = insertelement <4 x i8> %v01, i8 %i1, i32 1
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%v03 = insertelement <4 x i8> %v02, i8 %i2, i32 2
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%v = insertelement <4 x i8> %v03, i8 %i3, i32 3
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; Byte-wise add in the same block as the PHI (this must make coercion profitable).
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%acc.next = add <4 x i8> %acc, %v
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; Loop control.
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%i.next = add i32 %i, 4
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%cond = icmp slt i32 %i.next, %n
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; CHECK-LABEL: define amdgpu_kernel void @lro_coerce_v4i8_phi(
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; CHECK: loop:
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; CHECK: %i = phi i32
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; CHECK-NOT: phi <4 x i8>
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; CHECK: %[[ACCI32:[^ ]+]] = phi i32
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; CHECK-NEXT: %[[HDRCAST:[^ ]+]] = bitcast i32 %[[ACCI32]] to <4 x i8>
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; CHECK: add <4 x i8> %[[HDRCAST]],
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; CHECK: br i1
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