e95f6fa123
Introduce a target hook to incrementally flip the behavior of targets with test changes, and start by implementing it for AMDGPU. This appears to be forgotten switch flip from 2015. This seems to do a nicer job with subregister copies. Most of the test changes are improvements or neutral, not that many are light regressions. The worst AMDGPU regressions are for true16 in the atomic tests, but I think that's due to existing true16 issues.
845 lines
29 KiB
LLVM
845 lines
29 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
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define amdgpu_kernel void @test_umul24_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
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; SI-LABEL: test_umul24_i32:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_and_b32 s2, s4, 0xffffff
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; SI-NEXT: s_and_b32 s4, s5, 0xffffff
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; SI-NEXT: s_mul_i32 s4, s2, s4
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umul24_i32:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; VI-NEXT: s_and_b32 s4, s4, 0xffffff
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; VI-NEXT: s_and_b32 s5, s5, 0xffffff
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; VI-NEXT: s_mul_i32 s4, s4, s5
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umul24_i32:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GFX9-NEXT: s_and_b32 s4, s4, 0xffffff
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; GFX9-NEXT: s_and_b32 s5, s5, 0xffffff
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; GFX9-NEXT: s_mul_i32 s4, s4, s5
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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entry:
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%0 = shl i32 %a, 8
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%a_24 = lshr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = lshr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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store i32 %2, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_umul24_i16_sext(ptr addrspace(1) %out, i16 %a, i16 %b) {
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; SI-LABEL: test_umul24_i16_sext:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dword s2, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_lshr_b32 s4, s2, 16
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; SI-NEXT: s_mul_i32 s2, s2, s4
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; SI-NEXT: s_sext_i32_i16 s4, s2
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umul24_i16_sext:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dword s6, s[4:5], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_lshr_b32 s4, s6, 16
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; VI-NEXT: s_mul_i32 s6, s6, s4
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; VI-NEXT: s_sext_i32_i16 s4, s6
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umul24_i16_sext:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_lshr_b32 s4, s6, 16
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; GFX9-NEXT: s_mul_i32 s6, s6, s4
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; GFX9-NEXT: s_sext_i32_i16 s4, s6
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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entry:
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%mul = mul i16 %a, %b
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%ext = sext i16 %mul to i32
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store i32 %ext, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_umul24_i16_vgpr_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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; SI-LABEL: test_umul24_i16_vgpr_sext:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s10, 0
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; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
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; SI-NEXT: v_mov_b32_e32 v3, 0
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; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v1
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: v_mov_b32_e32 v1, v3
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
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; SI-NEXT: buffer_load_ushort v2, v[2:3], s[8:11], 0 addr64
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; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr64
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_mul_u32_u24_e32 v0, v2, v0
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; SI-NEXT: v_bfe_i32 v0, v0, 0, 16
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umul24_i16_vgpr_sext:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v3, s3
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; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v1
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_ushort v2, v[2:3]
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; VI-NEXT: flat_load_ushort v0, v[0:1]
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_mul_lo_u16_e32 v0, v2, v0
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; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umul24_i16_vgpr_sext:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]
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; GFX9-NEXT: global_load_ushort v3, v1, s[2:3]
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mul_lo_u16_e32 v0, v2, v3
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; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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%ptr_a = getelementptr i16, ptr addrspace(1) %in, i32 %tid.x
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%ptr_b = getelementptr i16, ptr addrspace(1) %in, i32 %tid.y
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%a = load i16, ptr addrspace(1) %ptr_a
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%b = load i16, ptr addrspace(1) %ptr_b
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%mul = mul i16 %a, %b
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%val = sext i16 %mul to i32
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_umul24_i16(ptr addrspace(1) %out, i16 %a, i16 %b) {
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; SI-LABEL: test_umul24_i16:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dword s2, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_lshr_b32 s4, s2, 16
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; SI-NEXT: s_mul_i32 s2, s2, s4
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; SI-NEXT: s_and_b32 s4, s2, 0xffff
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umul24_i16:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dword s6, s[4:5], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_lshr_b32 s4, s6, 16
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; VI-NEXT: s_mul_i32 s6, s6, s4
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; VI-NEXT: s_and_b32 s4, s6, 0xffff
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umul24_i16:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_lshr_b32 s4, s6, 16
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; GFX9-NEXT: s_mul_i32 s6, s6, s4
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; GFX9-NEXT: s_and_b32 s4, s6, 0xffff
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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entry:
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%mul = mul i16 %a, %b
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%ext = zext i16 %mul to i32
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store i32 %ext, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_umul24_i16_vgpr(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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; SI-LABEL: test_umul24_i16_vgpr:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s10, 0
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; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
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; SI-NEXT: v_mov_b32_e32 v3, 0
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; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v1
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: v_mov_b32_e32 v1, v3
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
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; SI-NEXT: buffer_load_ushort v2, v[2:3], s[8:11], 0 addr64
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; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr64
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_mul_u32_u24_e32 v0, v2, v0
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; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umul24_i16_vgpr:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v3, s3
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; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v1
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_ushort v2, v[2:3]
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; VI-NEXT: flat_load_ushort v0, v[0:1]
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_mul_lo_u16_e32 v0, v2, v0
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umul24_i16_vgpr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]
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; GFX9-NEXT: global_load_ushort v3, v1, s[2:3]
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mul_lo_u16_e32 v0, v2, v3
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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%ptr_a = getelementptr i16, ptr addrspace(1) %in, i32 %tid.x
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%ptr_b = getelementptr i16, ptr addrspace(1) %in, i32 %tid.y
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%a = load i16, ptr addrspace(1) %ptr_a
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%b = load i16, ptr addrspace(1) %ptr_b
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%mul = mul i16 %a, %b
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%val = zext i16 %mul to i32
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_umul24_i8_vgpr(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
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; SI-LABEL: test_umul24_i8_vgpr:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_mov_b32_e32 v3, v0
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
|
|
; SI-NEXT: s_mov_b32 s11, 0xf000
|
|
; SI-NEXT: v_mov_b32_e32 v4, 0
|
|
; SI-NEXT: s_mov_b32 s14, 0
|
|
; SI-NEXT: s_mov_b32 s15, s11
|
|
; SI-NEXT: v_mov_b32_e32 v2, v4
|
|
; SI-NEXT: s_mov_b64 s[6:7], s[14:15]
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: s_mov_b64 s[12:13], s[2:3]
|
|
; SI-NEXT: buffer_load_ubyte v0, v[3:4], s[12:15], 0 addr64
|
|
; SI-NEXT: buffer_load_ubyte v1, v[1:2], s[4:7], 0 addr64
|
|
; SI-NEXT: s_mov_b32 s10, -1
|
|
; SI-NEXT: s_mov_b32 s8, s0
|
|
; SI-NEXT: s_mov_b32 s9, s1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_mul_u32_u24_e32 v0, v0, v1
|
|
; SI-NEXT: v_bfe_i32 v0, v0, 0, 8
|
|
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: test_umul24_i8_vgpr:
|
|
; VI: ; %bb.0: ; %entry
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v3, s3
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v0
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: v_mov_b32_e32 v4, s5
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v1
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
|
|
; VI-NEXT: flat_load_ubyte v2, v[2:3]
|
|
; VI-NEXT: flat_load_ubyte v0, v[0:1]
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_mul_lo_u16_e32 v0, v2, v0
|
|
; VI-NEXT: v_bfe_i32 v0, v0, 0, 8
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: test_umul24_i8_vgpr:
|
|
; GFX9: ; %bb.0: ; %entry
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_ubyte v2, v0, s[2:3]
|
|
; GFX9-NEXT: global_load_ubyte v3, v1, s[6:7]
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_mul_lo_u16_e32 v0, v2, v3
|
|
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 8
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
entry:
|
|
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tid.y = call i32 @llvm.amdgcn.workitem.id.y()
|
|
%a.ptr = getelementptr i8, ptr addrspace(1) %a, i32 %tid.x
|
|
%b.ptr = getelementptr i8, ptr addrspace(1) %b, i32 %tid.y
|
|
%a.l = load i8, ptr addrspace(1) %a.ptr
|
|
%b.l = load i8, ptr addrspace(1) %b.ptr
|
|
%mul = mul i8 %a.l, %b.l
|
|
%ext = sext i8 %mul to i32
|
|
store i32 %ext, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_umulhi24_i32_i64(ptr addrspace(1) %out, i32 %a, i32 %b) {
|
|
; SI-LABEL: test_umulhi24_i32_i64:
|
|
; SI: ; %bb.0: ; %entry
|
|
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: s_mov_b32 s4, s0
|
|
; SI-NEXT: s_mov_b32 s5, s1
|
|
; SI-NEXT: v_mov_b32_e32 v0, s3
|
|
; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: test_umulhi24_i32_i64:
|
|
; VI: ; %bb.0: ; %entry
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v0, s3
|
|
; VI-NEXT: s_mov_b32 s4, s0
|
|
; VI-NEXT: s_mov_b32 s5, s1
|
|
; VI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0
|
|
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: test_umulhi24_i32_i64:
|
|
; GFX9: ; %bb.0: ; %entry
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_mov_b64 s[4:5], s[2:3]
|
|
; GFX9-NEXT: s_and_b32 s4, s4, 0xffffff
|
|
; GFX9-NEXT: s_and_b32 s5, s5, 0xffffff
|
|
; GFX9-NEXT: s_mul_hi_u32 s4, s4, s5
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
entry:
|
|
%a.24 = and i32 %a, 16777215
|
|
%b.24 = and i32 %b, 16777215
|
|
%a.24.i64 = zext i32 %a.24 to i64
|
|
%b.24.i64 = zext i32 %b.24 to i64
|
|
%mul48 = mul i64 %a.24.i64, %b.24.i64
|
|
%mul48.hi = lshr i64 %mul48, 32
|
|
%mul24hi = trunc i64 %mul48.hi to i32
|
|
store i32 %mul24hi, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_umulhi24(ptr addrspace(1) %out, i64 %a, i64 %b) {
|
|
; SI-LABEL: test_umulhi24:
|
|
; SI: ; %bb.0: ; %entry
|
|
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: s_load_dword s3, s[4:5], 0xd
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
; SI-NEXT: s_mov_b32 s4, s0
|
|
; SI-NEXT: s_mov_b32 s5, s1
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v0, s3
|
|
; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: test_umulhi24:
|
|
; VI: ; %bb.0: ; %entry
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: s_load_dword s3, s[4:5], 0x34
|
|
; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
; VI-NEXT: s_mov_b32 s4, s0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v0, s3
|
|
; VI-NEXT: s_mov_b32 s5, s1
|
|
; VI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0
|
|
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: test_umulhi24:
|
|
; GFX9: ; %bb.0: ; %entry
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_load_dword s3, s[4:5], 0x34
|
|
; GFX9-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s6, -1
|
|
; GFX9-NEXT: s_mov_b32 s4, s0
|
|
; GFX9-NEXT: s_mov_b32 s5, s1
|
|
; GFX9-NEXT: s_and_b32 s0, s2, 0xffffff
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_and_b32 s1, s3, 0xffffff
|
|
; GFX9-NEXT: s_mul_hi_u32 s0, s0, s1
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
entry:
|
|
%a.24 = and i64 %a, 16777215
|
|
%b.24 = and i64 %b, 16777215
|
|
%mul48 = mul i64 %a.24, %b.24
|
|
%mul48.hi = lshr i64 %mul48, 32
|
|
%mul24.hi = trunc i64 %mul48.hi to i32
|
|
store i32 %mul24.hi, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; Multiply with 24-bit inputs and 64-bit output.
|
|
define amdgpu_kernel void @test_umul24_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
|
|
; SI-LABEL: test_umul24_i64:
|
|
; SI: ; %bb.0: ; %entry
|
|
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: s_load_dword s3, s[4:5], 0xd
|
|
; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
; SI-NEXT: s_mov_b32 s6, -1
|
|
; SI-NEXT: s_mov_b32 s4, s0
|
|
; SI-NEXT: s_mov_b32 s5, s1
|
|
; SI-NEXT: s_and_b32 s0, s2, 0xffffff
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: s_and_b32 s1, s3, 0xffffff
|
|
; SI-NEXT: v_mov_b32_e32 v0, s3
|
|
; SI-NEXT: s_mul_i32 s0, s0, s1
|
|
; SI-NEXT: v_mul_hi_u32_u24_e32 v1, s2, v0
|
|
; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: test_umul24_i64:
|
|
; VI: ; %bb.0: ; %entry
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: s_load_dword s3, s[4:5], 0x34
|
|
; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
; VI-NEXT: s_mov_b32 s4, s0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v0, s3
|
|
; VI-NEXT: s_mov_b32 s5, s1
|
|
; VI-NEXT: v_mul_hi_u32_u24_e32 v1, s2, v0
|
|
; VI-NEXT: v_mul_u32_u24_e32 v0, s2, v0
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: test_umul24_i64:
|
|
; GFX9: ; %bb.0: ; %entry
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_load_dword s3, s[4:5], 0x34
|
|
; GFX9-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s6, -1
|
|
; GFX9-NEXT: s_mov_b32 s4, s0
|
|
; GFX9-NEXT: s_mov_b32 s5, s1
|
|
; GFX9-NEXT: s_and_b32 s0, s2, 0xffffff
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_and_b32 s1, s3, 0xffffff
|
|
; GFX9-NEXT: s_mul_hi_u32 s2, s0, s1
|
|
; GFX9-NEXT: s_mul_i32 s0, s0, s1
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s2
|
|
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
entry:
|
|
%tmp0 = shl i64 %a, 40
|
|
%a_24 = lshr i64 %tmp0, 40
|
|
%tmp1 = shl i64 %b, 40
|
|
%b_24 = lshr i64 %tmp1, 40
|
|
%tmp2 = mul i64 %a_24, %b_24
|
|
store i64 %tmp2, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define i64 @test_umul48_i64(i64 %lhs, i64 %rhs) {
|
|
; GCN-LABEL: test_umul48_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v2
|
|
; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v2
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
%lhs24 = and i64 %lhs, 16777215
|
|
%rhs24 = and i64 %rhs, 16777215
|
|
%mul = mul i64 %lhs24, %rhs24
|
|
ret i64 %mul
|
|
}
|
|
|
|
define <2 x i64> @test_umul48_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
|
|
; GCN-LABEL: test_umul48_v2i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v4
|
|
; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32_u24_e32 v3, v2, v6
|
|
; GCN-NEXT: v_mul_u32_u24_e32 v2, v2, v6
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
%lhs24 = and <2 x i64> %lhs, <i64 16777215, i64 16777215>
|
|
%rhs24 = and <2 x i64> %rhs, <i64 16777215, i64 16777215>
|
|
%mul = mul <2 x i64> %lhs24, %rhs24
|
|
ret <2 x i64> %mul
|
|
}
|
|
|
|
define amdgpu_kernel void @test_umul24_i64_square(ptr addrspace(1) %out, [8 x i32], i64 %a) {
|
|
; SI-LABEL: test_umul24_i64_square:
|
|
; SI: ; %bb.0: ; %entry
|
|
; SI-NEXT: s_load_dword s6, s[4:5], 0x13
|
|
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xffffff
|
|
; SI-NEXT: s_mul_i32 s4, s4, s4
|
|
; SI-NEXT: v_mul_hi_u32_u24_e64 v1, s6, s6
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: test_umul24_i64_square:
|
|
; VI: ; %bb.0: ; %entry
|
|
; VI-NEXT: s_load_dword s6, s[4:5], 0x4c
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mul_hi_u32_u24_e64 v1, s6, s6
|
|
; VI-NEXT: v_mul_u32_u24_e64 v0, s6, s6
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: test_umul24_i64_square:
|
|
; GFX9: ; %bb.0: ; %entry
|
|
; GFX9-NEXT: s_load_dword s6, s[4:5], 0x4c
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: s_and_b32 s4, s6, 0xffffff
|
|
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s4
|
|
; GFX9-NEXT: s_mul_i32 s4, s4, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
entry:
|
|
%tmp0 = shl i64 %a, 40
|
|
%a.24 = lshr i64 %tmp0, 40
|
|
%tmp2 = mul i64 %a.24, %a.24
|
|
store i64 %tmp2, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_umulhi16_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
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; SI-LABEL: test_umulhi16_i32:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_and_b32 s2, s4, 0xffff
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; SI-NEXT: s_and_b32 s4, s5, 0xffff
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; SI-NEXT: s_mul_i32 s2, s2, s4
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; SI-NEXT: s_lshr_b32 s4, s2, 16
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umulhi16_i32:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; VI-NEXT: s_and_b32 s4, s4, 0xffff
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; VI-NEXT: s_and_b32 s5, s5, 0xffff
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; VI-NEXT: s_mul_i32 s4, s4, s5
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; VI-NEXT: s_lshr_b32 s4, s4, 16
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umulhi16_i32:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
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; GFX9-NEXT: s_and_b32 s3, s3, 0xffff
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; GFX9-NEXT: s_mul_i32 s2, s2, s3
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; GFX9-NEXT: v_mov_b32_e32 v1, s2
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; GFX9-NEXT: global_store_short_d16_hi v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%a.16 = and i32 %a, 65535
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%b.16 = and i32 %b, 65535
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%mul = mul i32 %a.16, %b.16
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%hi = lshr i32 %mul, 16
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%mulhi = trunc i32 %hi to i16
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store i16 %mulhi, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_umul24_i33(ptr addrspace(1) %out, i33 %a, i33 %b) {
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; SI-LABEL: test_umul24_i33:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dword s4, s[4:5], 0xd
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_and_b32 s5, s6, 0xffffff
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; SI-NEXT: s_and_b32 s7, s4, 0xffffff
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s6, v0
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; SI-NEXT: s_mul_i32 s5, s5, s7
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; SI-NEXT: v_and_b32_e32 v1, 1, v0
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; SI-NEXT: v_mov_b32_e32 v0, s5
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umul24_i33:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dword s6, s[4:5], 0x34
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; VI-NEXT: s_load_dword s7, s[4:5], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s6
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; VI-NEXT: v_mul_u32_u24_e32 v0, s7, v1
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; VI-NEXT: v_mul_hi_u32_u24_e32 v1, s7, v1
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; VI-NEXT: v_and_b32_e32 v1, 1, v1
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umul24_i33:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dword s7, s[4:5], 0x34
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s4, s6, 0xffffff
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; GFX9-NEXT: s_and_b32 s5, s7, 0xffffff
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; GFX9-NEXT: s_mul_i32 s6, s4, s5
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; GFX9-NEXT: s_mul_hi_u32 s4, s4, s5
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; GFX9-NEXT: s_and_b32 s4, s4, 1
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; GFX9-NEXT: v_mov_b32_e32 v0, s6
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; GFX9-NEXT: v_mov_b32_e32 v1, s4
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; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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entry:
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%tmp0 = shl i33 %a, 9
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%a_24 = lshr i33 %tmp0, 9
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%tmp1 = shl i33 %b, 9
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%b_24 = lshr i33 %tmp1, 9
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%tmp2 = mul i33 %a_24, %b_24
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%ext = zext i33 %tmp2 to i64
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store i64 %ext, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_umulhi24_i33(ptr addrspace(1) %out, i33 %a, i33 %b) {
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; SI-LABEL: test_umulhi24_i33:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dword s6, s[4:5], 0xd
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; SI-NEXT: s_load_dword s7, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, s6
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; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s7, v0
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; SI-NEXT: v_and_b32_e32 v0, 1, v0
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_umulhi24_i33:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dword s6, s[4:5], 0x34
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; VI-NEXT: s_load_dword s7, s[4:5], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v0, s6
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; VI-NEXT: v_mul_hi_u32_u24_e32 v0, s7, v0
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; VI-NEXT: v_and_b32_e32 v0, 1, v0
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: test_umulhi24_i33:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dword s7, s[4:5], 0x34
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s4, s6, 0xffffff
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; GFX9-NEXT: s_and_b32 s5, s7, 0xffffff
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; GFX9-NEXT: s_mul_hi_u32 s4, s4, s5
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; GFX9-NEXT: s_and_b32 s4, s4, 1
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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entry:
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%tmp0 = shl i33 %a, 9
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%a_24 = lshr i33 %tmp0, 9
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%tmp1 = shl i33 %b, 9
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%b_24 = lshr i33 %tmp1, 9
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%tmp2 = mul i33 %a_24, %b_24
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%hi = lshr i33 %tmp2, 32
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%trunc = trunc i33 %hi to i32
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store i32 %trunc, ptr addrspace(1) %out
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ret void
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}
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; Make sure the created any_extend is ignored to use the real bits
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; being multiplied.
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define i17 @test_umul24_anyextend_i24_src0_src1(i24 %a, i24 %b) {
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; GCN-LABEL: test_umul24_anyextend_i24_src0_src1:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mul_u32_u24_e32 v0, 0xea, v0
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; GCN-NEXT: v_mul_u32_u24_e32 v1, 0x39b, v1
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; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v1
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; GCN-NEXT: v_and_b32_e32 v0, 0x1fffe, v0
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; GCN-NEXT: v_mul_u32_u24_e32 v0, 0x63, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%aa = mul i24 %a, 234
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%bb = mul i24 %b, 923
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%a_32 = zext i24 %aa to i32
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%b_32 = zext i24 %bb to i32
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%mul = mul i32 %a_32, %b_32
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%trunc = trunc i32 %mul to i17
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%arst = mul i17 %trunc, 99
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ret i17 %arst
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}
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define i17 @test_umul24_anyextend_i23_src0_src1(i23 %a, i23 %b) {
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; GCN-LABEL: test_umul24_anyextend_i23_src0_src1:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
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; GCN-NEXT: v_and_b32_e32 v1, 0x7fffff, v1
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; GCN-NEXT: v_mul_u32_u24_e32 v0, 0xea, v0
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; GCN-NEXT: v_mul_u32_u24_e32 v1, 0x39b, v1
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; GCN-NEXT: v_and_b32_e32 v0, 0x7ffffe, v0
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; GCN-NEXT: v_and_b32_e32 v1, 0x7fffff, v1
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; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v1
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; GCN-NEXT: v_and_b32_e32 v0, 0x1fffe, v0
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; GCN-NEXT: v_mul_u32_u24_e32 v0, 0x63, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%aa = mul i23 %a, 234
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%bb = mul i23 %b, 923
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%a_32 = zext i23 %aa to i32
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%b_32 = zext i23 %bb to i32
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%mul = mul i32 %a_32, %b_32
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%trunc = trunc i32 %mul to i17
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%arst = mul i17 %trunc, 99
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ret i17 %arst
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}
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