d226f1b161
Regenerate checks after two recent commits that caused extra stuff to be added at the end of assembly lines, so the existing checks did not fail. - #179414 added "nv" to loads and stores on GFX1250. - #185774 added "msbs" comments on setreg instructions.
36 lines
1.4 KiB
LLVM
36 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX12,GFX12-ISEL %s
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define amdgpu_kernel void @kernel1() #0 {
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; GFX12-LABEL: kernel1:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX12-NEXT: s_cmp_eq_u32 0, 0
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; GFX12-NEXT: s_barrier_signal_isfirst -1
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; GFX12-NEXT: s_barrier_wait -1
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; GFX12-NEXT: s_cselect_b32 s0, -1, 0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
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; GFX12-NEXT: s_cbranch_vccnz .LBB0_2
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; GFX12-NEXT: ; %bb.1:
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; GFX12-NEXT: s_barrier_signal -3
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; GFX12-NEXT: .LBB0_2:
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; GFX12-NEXT: s_barrier_wait -3
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; GFX12-NEXT: s_get_barrier_state s0, -3
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; GFX12-NEXT: s_endpgm
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call void @llvm.amdgcn.s.cluster.barrier()
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%state3 = call i32 @llvm.amdgcn.s.get.barrier.state(i32 -3)
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ret void
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}
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declare void @llvm.amdgcn.s.cluster.barrier() #1
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declare i32 @llvm.amdgcn.s.get.barrier.state(i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { convergent nounwind }
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attributes #2 = { nounwind readnone }
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GFX12-ISEL: {{.*}}
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; GFX12-SDAG: {{.*}}
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