9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
51 lines
2.2 KiB
YAML
51 lines
2.2 KiB
YAML
# RUN: llc -mtriple=amdgcn -run-pass machine-scheduler -verify-machineinstrs %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# CHECK: SU(0): $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec
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# CHECK: Successors:
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# CHECK-NEXT: SU(2): Out Latency=1
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# CHECK-NEXT: SU(2): Data Latency=1 Reg=$vgpr0
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# CHECK: SU(1): $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec
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# CHECK: Successors:
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# CHECK-NEXT: SU(3): Out Latency=1
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# CHECK-NEXT: SU(3): Data Latency=1 Reg=$vgpr1
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# CHECK: SU(2): $vgpr0 = V_ADD_CO_U32_e32 $sgpr2, $vgpr0, implicit-def $vcc, implicit $exec
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# CHECK: Predecessors:
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# CHECK-NEXT: SU(0): Out Latency=1
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# CHECK-NEXT: SU(0): Data Latency=1 Reg=$vgpr0
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# CHECK: Successors:
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# CHECK-NEXT: SU(4): Out Latency=1
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# CHECK-NEXT: SU(4): Data Latency=1 Reg=$vgpr0_vgpr1
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# CHECK-NEXT: SU(3): Out Latency=1
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# CHECK-NEXT: SU(3): Data Latency=1 Reg=$vcc
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# CHECK: SU(3): $vgpr1 = V_ADDC_U32_e32 0, $vgpr1, implicit-def dead $vcc, implicit $vcc, implicit $exec
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# CHECK: Predecessors:
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# CHECK-NEXT: SU(2): Out Latency=1
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# CHECK-NEXT: SU(2): Data Latency=1 Reg=$vcc
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# CHECK-NEXT: SU(1): Out Latency=1
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# CHECK-NEXT: SU(1): Data Latency=1 Reg=$vgpr1
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# CHECK: Successors:
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# CHECK-NEXT: SU(4): Out Latency=1
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# CHECK-NEXT: SU(4): Data Latency=1 Reg=$vgpr0_vgpr1
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# CHECK: SU(4): $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
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# CHECK: Predecessors:
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# CHECK-NEXT: SU(3): Out Latency=1
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# CHECK-NEXT: SU(3): Data Latency=1 Reg=$vgpr0_vgpr1
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# CHECK-NEXT: SU(2): Out Latency=1
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# CHECK-NEXT: SU(2): Data Latency=1 Reg=$vgpr0_vgpr1
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# CHECK: Successors:
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# CHECK-NEXT: ExitSU: Ord Latency=3 Artificial
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---
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name: test
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec
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$vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec
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$vgpr0 = V_ADD_CO_U32_e32 $sgpr2, $vgpr0, implicit-def $vcc, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 0, $vgpr1, implicit-def dead $vcc, implicit $vcc, implicit $exec
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$vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
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...
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