0e1cb2de90
This reverts commit 6d5f87fc4284c4c22512778afaf7f2ba9326ba7b. Previously this failed due to treating the unknown MachineMemOperand value as known uniform.
127 lines
4.9 KiB
LLVM
127 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
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define i32 @select_load_i32_p0(i1 %cond, ptr %a, ptr %b) {
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; CHECK-LABEL: select_load_i32_p0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
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; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; CHECK-NEXT: flat_load_dword v0, v[1:2]
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ld0 = load i32, ptr %a
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%ld1 = load i32, ptr %b
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%select = select i1 %cond, i32 %ld0, i32 %ld1
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ret i32 %select
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}
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define i32 @select_load_i32_p1(i1 %cond, ptr addrspace(1) %a, ptr addrspace(1) %b) {
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; CHECK-LABEL: select_load_i32_p1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
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; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; CHECK-NEXT: global_load_dword v0, v[1:2], off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ld0 = load i32, ptr addrspace(1) %a
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%ld1 = load i32, ptr addrspace(1) %b
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%select = select i1 %cond, i32 %ld0, i32 %ld1
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ret i32 %select
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}
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define i32 @select_load_i32_p3(i1 %cond, ptr addrspace(3) %a, ptr addrspace(3) %b) {
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; CHECK-LABEL: select_load_i32_p3:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
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; CHECK-NEXT: ds_read_b32 v0, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ld0 = load i32, ptr addrspace(3) %a
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%ld1 = load i32, ptr addrspace(3) %b
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%select = select i1 %cond, i32 %ld0, i32 %ld1
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ret i32 %select
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}
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define i32 @select_load_i32_p0_p1(i1 %cond, ptr %a, ptr addrspace(1) %b) {
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; CHECK-LABEL: select_load_i32_p0_p1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: flat_load_dword v5, v[1:2]
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; CHECK-NEXT: global_load_dword v6, v[3:4], off
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ld0 = load i32, ptr %a
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%ld1 = load i32, ptr addrspace(1) %b
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%select = select i1 %cond, i32 %ld0, i32 %ld1
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ret i32 %select
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}
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define i32 @select_load_i32_p1_p0(i1 %cond, ptr addrspace(1) %a, ptr %b) {
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; CHECK-LABEL: select_load_i32_p1_p0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: global_load_dword v5, v[1:2], off
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; CHECK-NEXT: flat_load_dword v6, v[3:4]
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ld0 = load i32, ptr addrspace(1) %a
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%ld1 = load i32, ptr %b
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%select = select i1 %cond, i32 %ld0, i32 %ld1
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ret i32 %select
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}
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define i8 @select_load_i8_p1(i1 %cond, ptr addrspace(1) %a, ptr addrspace(1) %b) {
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; CHECK-LABEL: select_load_i8_p1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
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; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
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; CHECK-NEXT: global_load_ubyte v0, v[1:2], off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%ld0 = load i8, ptr addrspace(1) %a
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%ld1 = load i8, ptr addrspace(1) %b
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%select = select i1 %cond, i8 %ld0, i8 %ld1
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ret i8 %select
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}
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define i32 @select_load_i32_p1_offset(i1 %cond, ptr addrspace(1) %a, ptr addrspace(1) %b) {
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; CHECK-LABEL: select_load_i32_p1_offset:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_add_co_u32_e32 v3, vcc, 0x100, v1
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; CHECK-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v2, vcc
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; CHECK-NEXT: v_add_co_u32_e32 v5, vcc, 0x200, v1
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
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; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%gep.a = getelementptr i8, ptr addrspace(1) %a, i64 256
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%gep.b = getelementptr i8, ptr addrspace(1) %a, i64 512
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%ld0 = load i32, ptr addrspace(1) %gep.a
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%ld1 = load i32, ptr addrspace(1) %gep.b
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%select = select i1 %cond, i32 %ld0, i32 %ld1
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ret i32 %select
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}
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