7274ae970d
When scheduling must be reverted for a region, the current implementation re-orders non-debug instructions and debug instructions separately; the former in a first pass and the latter in a second pass handled by a generic machine scheduler helper whose state is tied to the current region being scheduled, in turns limiting the revert logic to only work on the active scheduling region. This makes the revert logic work in a single pass for all MIs, and removes the restriction that it works exclusively on the active scheduling region. The latter enables future use cases such as reverting scheduling of multiple regions at once.
19 lines
619 B
LLVM
19 lines
619 B
LLVM
; REQUIRES: asserts
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; RUN: llc -mtriple=amdgcn -O1 -mcpu=gfx90a -debug-only=machine-scheduler -filetype=null < %s 2>&1 | FileCheck --check-prefix=DEBUG %s
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; DEBUG: Reverting scheduling for region 0
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@G = global <32 x i8> splat (i8 1)
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@G.1 = global <32 x i8> splat (i8 127)
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define amdgpu_kernel void @gws_sema_v_offset0(i32 %val, <32 x i1>* %inp) {
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%LGV1 = load <32 x i8>, ptr @G.1, align 32
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%LGV = load <32 x i8>, ptr @G, align 32
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call void @llvm.amdgcn.ds.gws.sema.v(i32 0)
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%C = icmp ne <32 x i8> %LGV, %LGV1
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store <32 x i1> %C, ptr %inp, align 4
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ret void
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}
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declare void @llvm.amdgcn.ds.gws.sema.v(i32)
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