148 lines
5.1 KiB
LLVM
148 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -p simplifycfg,amdgpu-unify-divergent-exit-nodes %s -S -o - | FileCheck %s --check-prefix=OPT
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; RUN: llc -mtriple=amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefix=ISA
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define void @nested_inf_loop(i1 %0, i1 %1) {
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; OPT-LABEL: define void @nested_inf_loop(
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; OPT-SAME: i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {
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; OPT-NEXT: [[BB:.*:]]
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; OPT-NEXT: br label %[[BB1:.*]]
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; OPT: [[BB1]]:
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; OPT-NEXT: [[BRMERGE:%.*]] = select i1 [[TMP0]], i1 true, i1 [[TMP1]]
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; OPT-NEXT: br i1 [[BRMERGE]], label %[[BB1]], label %[[INFLOOP:.*]]
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; OPT: [[INFLOOP]]:
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; OPT-NEXT: br i1 true, label %[[INFLOOP]], label %[[DUMMYRETURNBLOCK:.*]]
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; OPT: [[DUMMYRETURNBLOCK]]:
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; OPT-NEXT: ret void
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;
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; ISA-LABEL: nested_inf_loop:
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; ISA: ; %bb.0: ; %BB
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; ISA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; ISA-NEXT: v_and_b32_e32 v1, 1, v1
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; ISA-NEXT: v_and_b32_e32 v0, 1, v0
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; ISA-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
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; ISA-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, v0
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; ISA-NEXT: s_mov_b64 s[8:9], 0
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; ISA-NEXT: .LBB0_1: ; %BB1
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; ISA-NEXT: ; =>This Loop Header: Depth=1
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; ISA-NEXT: ; Child Loop BB0_3 Depth 2
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; ISA-NEXT: s_and_b64 s[10:11], exec, s[6:7]
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; ISA-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
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; ISA-NEXT: s_andn2_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_cbranch_execnz .LBB0_1
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; ISA-NEXT: ; %bb.2: ; %BB2
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; ISA-NEXT: ; in Loop: Header=BB0_1 Depth=1
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; ISA-NEXT: s_or_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_mov_b64 s[8:9], 0
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; ISA-NEXT: .LBB0_3: ; %BB4
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; ISA-NEXT: ; Parent Loop BB0_1 Depth=1
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; ISA-NEXT: ; => This Inner Loop Header: Depth=2
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; ISA-NEXT: s_and_b64 s[10:11], exec, s[4:5]
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; ISA-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
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; ISA-NEXT: s_andn2_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_cbranch_execnz .LBB0_3
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; ISA-NEXT: ; %bb.4: ; %loop.exit.guard
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; ISA-NEXT: ; in Loop: Header=BB0_1 Depth=1
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; ISA-NEXT: s_or_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_mov_b64 vcc, 0
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; ISA-NEXT: s_mov_b64 s[8:9], 0
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; ISA-NEXT: s_branch .LBB0_1
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; ISA-NEXT: ; %bb.5: ; %DummyReturnBlock
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; ISA-NEXT: s_setpc_b64 s[30:31]
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BB:
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br label %BB1
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BB1:
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br i1 %0, label %BB3, label %BB2
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BB2:
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br label %BB4
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BB4:
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br i1 %1, label %BB3, label %BB4
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BB3:
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br label %BB1
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}
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define void @nested_inf_loop_callbr(i32 %0, i32 %1) {
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; OPT-LABEL: define void @nested_inf_loop_callbr(
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; OPT-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]]) {
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; OPT-NEXT: [[BB:.*:]]
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; OPT-NEXT: callbr void asm "", ""()
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; OPT-NEXT: to label %[[BB1:.*]] []
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; OPT: [[BB1]]:
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; OPT-NEXT: callbr void asm "", "r,!i"(i32 [[TMP0]])
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; OPT-NEXT: to label %[[BB3:.*]] [label %BB2]
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; OPT: [[BB2:.*:]]
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; OPT-NEXT: callbr void asm "", ""()
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; OPT-NEXT: to label %[[BB4:.*]] []
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; OPT: [[BB4]]:
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; OPT-NEXT: br i1 true, label %[[TRANSITIONBLOCK:.*]], label %[[DUMMYRETURNBLOCK:.*]]
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; OPT: [[TRANSITIONBLOCK]]:
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; OPT-NEXT: callbr void asm "", "r,!i"(i32 [[TMP1]])
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; OPT-NEXT: to label %[[BB3]] [label %BB4]
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; OPT: [[BB3]]:
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; OPT-NEXT: callbr void asm "", ""()
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; OPT-NEXT: to label %[[BB1]] []
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; OPT: [[DUMMYRETURNBLOCK]]:
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; OPT-NEXT: ret void
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;
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; ISA-LABEL: nested_inf_loop_callbr:
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; ISA: ; %bb.0: ; %BB
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; ISA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; ISA-NEXT: ;;#ASMSTART
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; ISA-NEXT: ;;#ASMEND
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; ISA-NEXT: ; implicit-def: $sgpr6_sgpr7
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; ISA-NEXT: ; implicit-def: $sgpr4_sgpr5
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; ISA-NEXT: .LBB1_1: ; %BB1
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; ISA-NEXT: ; =>This Inner Loop Header: Depth=1
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; ISA-NEXT: ;;#ASMSTART
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; ISA-NEXT: ;;#ASMEND
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; ISA-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
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; ISA-NEXT: s_and_b64 s[8:9], s[4:5], exec
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; ISA-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
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; ISA-NEXT: .LBB1_2: ; %BB3
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; ISA-NEXT: ; in Loop: Header=BB1_1 Depth=1
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; ISA-NEXT: ;;#ASMSTART
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; ISA-NEXT: ;;#ASMEND
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; ISA-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
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; ISA-NEXT: s_and_b64 s[8:9], s[6:7], exec
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; ISA-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
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; ISA-NEXT: s_branch .LBB1_1
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; ISA-NEXT: .LBB1_3: ; Inline asm indirect target
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; ISA-NEXT: ; %BB2
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; ISA-NEXT: ; in Loop: Header=BB1_1 Depth=1
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; ISA-NEXT: ; Label of block must be emitted
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; ISA-NEXT: ;;#ASMSTART
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; ISA-NEXT: ;;#ASMEND
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; ISA-NEXT: s_mov_b64 s[6:7], -1
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; ISA-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
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; ISA-NEXT: s_cbranch_execz .LBB1_5
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; ISA-NEXT: ; %bb.4: ; %TransitionBlock.target.BB3
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; ISA-NEXT: ; in Loop: Header=BB1_1 Depth=1
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; ISA-NEXT: s_xor_b64 s[6:7], exec, -1
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; ISA-NEXT: .LBB1_5: ; %loop.exit.guard
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; ISA-NEXT: ; in Loop: Header=BB1_1 Depth=1
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; ISA-NEXT: s_or_b64 exec, exec, s[8:9]
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; ISA-NEXT: s_and_b64 vcc, exec, s[6:7]
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; ISA-NEXT: s_mov_b64 s[6:7], 0
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; ISA-NEXT: s_cbranch_vccz .LBB1_2
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; ISA-NEXT: ; %bb.6: ; %DummyReturnBlock
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; ISA-NEXT: s_setpc_b64 s[30:31]
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BB:
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callbr void asm "", ""() to label %BB1 []
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BB1:
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callbr void asm "", "r,!i"(i32 %0) to label %BB3 [label %BB2]
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BB2:
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callbr void asm "", ""() to label %BB4 []
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BB4:
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callbr void asm "", "r,!i"(i32 %1) to label %BB3 [label %BB4]
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BB3:
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callbr void asm "", ""() to label %BB1 []
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}
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