shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/store-to-constant.ll
Drew Kersnar 9c78bc5de4
Revert "[LSV] Merge contiguous chains across scalar types" (#170381) 
Reverts llvm/llvm-project#154069. I pointed out a number of issues
post-merge, most importantly examples of miscompiles:
https://github.com/llvm/llvm-project/pull/154069#issuecomment-3603854626.

While the motivation of the change is clear, I think the implementation
approach is flawed. It seems like the goal is to allow elements like
`load <2xi16>` and `load i32` to be vectorized together despite the
current algorithm not grouping them into the same equivalence classes. I
personally think that if we want to attempt this it should be a more
wholistic approach, maybe even redefining the concept of an equivalence
class. This current solution seems like it would be really hard to do
bug-free, and even if the bugs were not present, it is only able to
merge chains that happen to be adjacent to each other after
`splitChainByContiguity`, which seems like it is leaving things up to
chance whether this optimization kicks in. But we can discuss more in
the re-land. Maybe the broader approach I'm proposing is too difficult,
and a narrow optimization is worthwhile. Regardless, this should be
reverted, it needs more iteration before it is correct.
2025-12-02 18:27:58 -05:00

187 lines
6.5 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o - | FileCheck %s
; FIXME: We need to test AS6 but the AS6 variants of the following tests fail because of illegal VGPR to SGPR copy.
; FIXME: We also want to test memset, memcpy, and memmove, but it needs to fix the SelectionDAG store merging issue (#90714).
define amdgpu_kernel void @store_as4_i8(ptr addrspace(4) %p, i8 %v) {
; CHECK-LABEL: store_as4_i8:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_byte v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store i8 %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_i16(ptr addrspace(4) %p, i16 %v) {
; CHECK-LABEL: store_as4_i16:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_short v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store i16 %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_i32(ptr addrspace(4) %p, i32 %v) {
; CHECK-LABEL: store_as4_i32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store i32 %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_i64(ptr addrspace(4) %p, i64 %v) {
; CHECK-LABEL: store_as4_i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v2, s2
; CHECK-NEXT: v_mov_b32_e32 v3, s3
; CHECK-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
; CHECK-NEXT: s_endpgm
store i64 %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_float(ptr addrspace(4) %p, float %v) {
; CHECK-LABEL: store_as4_float:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store float %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_double(ptr addrspace(4) %p, double %v) {
; CHECK-LABEL: store_as4_double:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v2, s2
; CHECK-NEXT: v_mov_b32_e32 v3, s3
; CHECK-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
; CHECK-NEXT: s_endpgm
store double %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_half(ptr addrspace(4) %p, half %v) {
; CHECK-LABEL: store_as4_half:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_short v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store half %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_2xi8(ptr addrspace(4) %p, <2 x i8> %v) {
; CHECK-LABEL: store_as4_2xi8:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_short v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store <2 x i8> %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_2xi16(ptr addrspace(4) %p, <2 x i16> %v) {
; CHECK-LABEL: store_as4_2xi16:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store <2 x i16> %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_2xi32(ptr addrspace(4) %p, <2 x i32> %v) {
; CHECK-LABEL: store_as4_2xi32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; CHECK-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
; CHECK-NEXT: s_endpgm
store <2 x i32> %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_2xhalf(ptr addrspace(4) %p, <2 x half> %v) {
; CHECK-LABEL: store_as4_2xhalf:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s2
; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
; CHECK-NEXT: s_endpgm
store <2 x half> %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_2xfloat(ptr addrspace(4) %p, <2 x float> %v) {
; CHECK-LABEL: store_as4_2xfloat:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; CHECK-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
; CHECK-NEXT: s_endpgm
store <2 x float> %v, ptr addrspace(4) %p
ret void
}
define amdgpu_kernel void @store_as4_2xdouble(ptr addrspace(4) %p, <2 x double> %v) {
; CHECK-LABEL: store_as4_2xdouble:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_pk_mov_b32 v[4:5], s[2:3], s[2:3] op_sel:[0,1]
; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
; CHECK-NEXT: global_store_dwordx4 v0, v[2:5], s[4:5]
; CHECK-NEXT: s_endpgm
store <2 x double> %v, ptr addrspace(4) %p
ret void
}
Reference in New Issue View Git Blame Copy Permalink