36445f7b8f
On the callee side, `LowerFormalArguments` marks SGPR0-3 as allocated in `CCState` before running the CC analysis. On the caller side, `LowerCall` (and GlobalISel's `lowerCall`/`lowerTailCall`) added the scratch resource to `RegsToPass` without marking it in `CCState`. This caused `CC_AMDGPU_Func` to treat SGPR0-3 as available on the caller side, assigning user inreg args there, while the callee skipped them without marking it in `CCState`. This caused `CC_AMDGPU_Func` to treat SGPR0-3 as available on the caller side, assigning user inreg args there, while the callee skipped them.
69 lines
2.7 KiB
LLVM
69 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
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declare hidden void @void_func_i32_inreg(i32 inreg)
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define void @tail_call_i32_inreg_uniform(i32 inreg %sgpr) {
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; CHECK-LABEL: tail_call_i32_inreg_uniform:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[18:19]
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; CHECK-NEXT: s_add_u32 s18, s18, void_func_i32_inreg@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s19, s19, void_func_i32_inreg@rel32@hi+12
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; CHECK-NEXT: s_setpc_b64 s[18:19]
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tail call void @void_func_i32_inreg(i32 inreg %sgpr)
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ret void
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}
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@constant = external hidden addrspace(4) constant ptr
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define void @indirect_tail_call_i32_inreg_uniform(i32 inreg %sgpr) {
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; CHECK-LABEL: indirect_tail_call_i32_inreg_uniform:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[18:19]
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; CHECK-NEXT: s_add_u32 s18, s18, constant@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s19, s19, constant@rel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[18:19], s[18:19], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[18:19]
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%fptr = load ptr, ptr addrspace(4) @constant, align 8
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tail call void %fptr(i32 inreg %sgpr)
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ret void
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}
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declare void @void_func_i64_inreg(i64 inreg)
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define void @tail_call_i64_inreg_uniform(i64 inreg %sgpr) {
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; CHECK-LABEL: tail_call_i64_inreg_uniform:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[18:19]
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; CHECK-NEXT: s_add_u32 s18, s18, void_func_i64_inreg@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s19, s19, void_func_i64_inreg@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[18:19], s[18:19], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[18:19]
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tail call void @void_func_i64_inreg(i64 inreg %sgpr)
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ret void
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}
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define void @tail_call_i64_inreg_uniform_in_vgpr() {
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; CHECK-LABEL: tail_call_i64_inreg_uniform_in_vgpr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ds_read_b64 v[0:1], v0
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, void_func_i64_inreg@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, void_func_i64_inreg@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[18:19], s[16:17], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s16, v0
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; CHECK-NEXT: v_readfirstlane_b32 s17, v1
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; CHECK-NEXT: s_setpc_b64 s[18:19]
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%uniform.vgpr = load i64, ptr addrspace(3) zeroinitializer, align 8
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tail call void @void_func_i64_inreg(i64 inreg %uniform.vgpr)
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ret void
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}
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