694a488708
64-bit version of 7425af4b7aaa31da10bd1bc7996d3bb212c79d88. We still need to lower to 32-bit v_accagpr_write_b32s, so this has a unique value restriction that requires both halves of the constant to be 32-bit inline immediates. This only introduces the new pseudo definitions, but doesn't try to use them yet.
183 lines
7.3 KiB
YAML
183 lines
7.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=register-coalescer -o - %s | FileCheck %s
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# Check that we get two move-immediates into %1 and %2, instead of a copy from
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# %1 to %2, because that would introduce a dependency and maybe a stall.
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---
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name: remat_v_mov_b32_e32
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: remat_v_mov_b32_e32
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0
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; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MUL_F32_e32 [[V_MOV_B32_e32_]].sub0, [[V_MOV_B32_e32_]].sub0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MUL_F32_e32 [[V_MOV_B32_e32_]].sub1, [[V_MOV_B32_e32_]].sub1, implicit $mode, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
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bb.0:
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liveins: $sgpr0
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%1:vgpr_32 = COPY %0:vgpr_32
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%2:vgpr_32 = COPY %0:vgpr_32
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%3:sreg_64 = COPY $sgpr0
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$exec = S_MOV_B64_term %3:sreg_64
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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%1:vgpr_32 = V_MUL_F32_e32 %1:vgpr_32, %1:vgpr_32, implicit $mode, implicit $exec
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%2:vgpr_32 = V_MUL_F32_e32 %2:vgpr_32, %2:vgpr_32, implicit $mode, implicit $exec
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bb.2:
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undef %4.sub0:vreg_96 = COPY %1:vgpr_32
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%4.sub1:vreg_96 = COPY %2:vgpr_32
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S_ENDPGM 0, implicit %4
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...
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---
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name: remat_v_mov_b64_pseudo
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: remat_v_mov_b64_pseudo
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[V_MOV_B:%[0-9]+]].sub0_sub1:vreg_192_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub2_sub3:vreg_192_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub0_sub1:vreg_192_align2 = V_MUL_F64_e64 0, [[V_MOV_B]].sub0_sub1, 0, [[V_MOV_B]].sub0_sub1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub2_sub3:vreg_192_align2 = V_MUL_F64_e64 0, [[V_MOV_B]].sub2_sub3, 0, [[V_MOV_B]].sub2_sub3, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MOV_B]]
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bb.0:
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liveins: $sgpr0
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%0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
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%1:vreg_64_align2 = COPY %0:vreg_64_align2
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%2:vreg_64_align2 = COPY %0:vreg_64_align2
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%3:sreg_64 = COPY $sgpr0_sgpr1
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$exec = S_MOV_B64_term %3:sreg_64
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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%1:vreg_64_align2 = V_MUL_F64_e64 0, %1:vreg_64_align2, 0, %1:vreg_64_align2, 0, 0, implicit $mode, implicit $exec
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%2:vreg_64_align2 = V_MUL_F64_e64 0, %2:vreg_64_align2, 0, %2:vreg_64_align2, 0, 0, implicit $mode, implicit $exec
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bb.2:
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undef %4.sub0_sub1:vreg_192 = COPY %1:vreg_64_align2
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%4.sub2_sub3:vreg_192 = COPY %2:vreg_64_align2
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S_ENDPGM 0, implicit %4
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...
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---
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name: av_mov_imm_b32
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: av_mov_imm_b32
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0:vreg_96 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
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; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub1:vreg_96 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0
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; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub0:vreg_96 = V_MUL_F32_e32 [[AV_MOV_]].sub0, [[AV_MOV_]].sub0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub1:vreg_96 = V_MUL_F32_e32 [[AV_MOV_]].sub1, [[AV_MOV_]].sub1, implicit $mode, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
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bb.0:
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liveins: $sgpr0
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%0:av_32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
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%1:vgpr_32 = COPY %0
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%2:vgpr_32 = COPY %0
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%3:sreg_64 = COPY $sgpr0
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$exec = S_MOV_B64_term %3:sreg_64
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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%1:vgpr_32 = V_MUL_F32_e32 %1:vgpr_32, %1:vgpr_32, implicit $mode, implicit $exec
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%2:vgpr_32 = V_MUL_F32_e32 %2:vgpr_32, %2:vgpr_32, implicit $mode, implicit $exec
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bb.2:
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undef %4.sub0:vreg_96 = COPY %1:vgpr_32
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%4.sub1:vreg_96 = COPY %2:vgpr_32
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S_ENDPGM 0, implicit %4
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...
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---
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name: av_mov_imm_b64
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: av_mov_imm_b64
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $sgpr0_sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0_sub1:vreg_192 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
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; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub2_sub3:vreg_192 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub0_sub1:vreg_192 = V_MUL_F64_e64 0, [[AV_MOV_]].sub0_sub1, 0, [[AV_MOV_]].sub0_sub1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub2_sub3:vreg_192 = V_MUL_F64_e64 0, [[AV_MOV_]].sub2_sub3, 0, [[AV_MOV_]].sub2_sub3, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:av_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
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%1:vreg_64 = COPY %0
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%2:vreg_64 = COPY %0
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%3:sreg_64 = COPY $sgpr0_sgpr1
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$exec = S_MOV_B64_term %3:sreg_64
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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%1:vreg_64 = V_MUL_F64_e64 0, %1:vreg_64, 0, %1:vreg_64, 0, 0, implicit $mode, implicit $exec
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%2:vreg_64 = V_MUL_F64_e64 0, %2:vreg_64, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec
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bb.2:
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undef %4.sub0_sub1:vreg_192 = COPY %1:vreg_64
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%4.sub2_sub3:vreg_192 = COPY %2:vreg_64
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S_ENDPGM 0, implicit %4
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...
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