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llvm-project/llvm/lib/CodeGen/SelectionDAG
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chenglin.bi be7d0d6db5 [DAGCombiner] Fix issue with rot chain pattern 
faa35fc87370 fix the case of negative input shift. But when `c1`, `c2` is not the same side, it will also cause negative shift amount.
And that negative shift amount can't normalize by urem. So add one more bit size to normalize the last shift amount.

Fix: https://github.com/llvm/llvm-project/issues/59898

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D141363
2023-01-11 01:29:09 +08:00
..
CMakeLists.txt
[Support] Move TargetParsers to new component
2022-12-20 11:05:50 +00:00
DAGCombiner.cpp
[DAGCombiner] Fix issue with rot chain pattern
2023-01-11 01:29:09 +08:00
FastISel.cpp
[DebugInfo] Produce variadic DBG_INSTR_REFs from ISel
2023-01-09 08:58:33 +00:00
FunctionLoweringInfo.cpp
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
InstrEmitter.cpp
[llvm] Fix an "unused variable" warning when assertions are disabled
2023-01-09 11:33:05 +01:00
InstrEmitter.h
[DebugInfo] Produce variadic DBG_INSTR_REFs from ISel
2023-01-09 08:58:33 +00:00
LegalizeDAG.cpp
[Intrinsic] Rename flt.rounds intrinsic to get.rounding
2022-12-19 15:22:39 +08:00
LegalizeFloatTypes.cpp
[SelectionDAG] Rewrite bfloat16 softening to use the "half promotion" path
2022-09-06 11:54:34 +02:00
LegalizeIntegerTypes.cpp
[SelectionDAG][AVR] Add support for lrint and lround intrinsics
2023-01-08 18:56:07 +01:00
LegalizeTypes.cpp
[X86] Allow no X87 on 32-bit
2022-11-22 10:47:47 +08:00
LegalizeTypes.h
[SelectionDAG][AVR] Add support for lrint and lround intrinsics
2023-01-08 18:56:07 +01:00
LegalizeTypesGeneric.cpp
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
2023-01-05 14:11:08 +01:00
LegalizeVectorOps.cpp
[VP][RISCV] Add vp.ctlz/cttz and RISC-V support.
2023-01-04 15:15:01 +08:00
LegalizeVectorTypes.cpp
[VP][RISCV] Add vp.abs and RISC-V support.
2023-01-06 15:18:12 +08:00
ResourcePriorityQueue.cpp
Remove unneeded cl::ZeroOrMore for cl::opt/cl::list options
2022-06-05 00:31:44 -07:00
ScheduleDAGFast.cpp
[MC] Consistently use MCInstrDesc::getImplicitUses and getImplicitDefs. NFC.
2023-01-04 13:16:12 +00:00
ScheduleDAGRRList.cpp
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
2023-01-05 14:11:08 +01:00
ScheduleDAGSDNodes.cpp
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
2023-01-05 14:11:08 +01:00
ScheduleDAGSDNodes.h
[CodeGen] Use default member initialization (NFC)
2022-01-30 12:32:51 -08:00
ScheduleDAGVLIW.cpp
Cleanup includes: DebugInfo & CodeGen
2022-03-12 17:26:40 +01:00
SDNodeDbgValue.h
Cleanup includes: DebugInfo & CodeGen
2022-03-12 17:26:40 +01:00
SelectionDAG.cpp
[SelectionDAG] Implicitly truncate known bits in SPLAT_VECTOR
2023-01-06 15:43:47 +00:00
SelectionDAGAddressAnalysis.cpp
[CodeGen] llvm::Optional => std::optional
2022-12-13 09:06:36 +00:00
SelectionDAGBuilder.cpp
[DebugInfo] Produce variadic DBG_INSTR_REFs from ISel
2023-01-09 08:58:33 +00:00
SelectionDAGBuilder.h
[Assignment Tracking][Analysis] Add analysis pass
2022-12-09 16:17:37 +00:00
SelectionDAGDumper.cpp
[SDAG] Introduce a common MEMBARRIER node [nfc]
2023-01-09 15:20:08 -08:00
SelectionDAGISel.cpp
[DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
2023-01-06 18:03:48 +00:00
SelectionDAGPrinter.cpp
Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"
2022-04-06 20:32:53 +03:00
SelectionDAGTargetInfo.cpp
…
StatepointLowering.cpp
[CodeGen] std::optional::value => operator*/operator->
2022-12-16 23:41:36 +00:00
StatepointLowering.h
…
TargetLowering.cpp
[SDAG] try to avoid multiply for X*Y==0
2023-01-06 09:06:11 -05:00