Stanislav Mekhanoshin fa48c496e2 [AMDGPU] Shrinking V_SUBBREV_U32 ...

V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when
we try to commute V_SUBB_U32 in order to shrink it we do not then
process V_SUBBREV_U32 and it stay VOP3. This is fixed.

Differential Revision: https://reviews.llvm.org/D43699

llvm-svn: 326011

2018-02-24 01:32:32 +00:00

..

AArch64

[PATCH] [AArch64] Add new target feature to fuse conditional select

2018-02-23 19:27:43 +00:00

AMDGPU

[AMDGPU] Shrinking V_SUBBREV_U32

2018-02-24 01:32:32 +00:00

ARC

…

ARM

Recommit: [ARM] f16 constant pool fix

2018-02-22 10:43:57 +00:00

AVR

[CodeGen] Unify the syntax of MBB successors in MIR and -debug output

2018-02-09 00:10:31 +00:00

BPF

bpf: New codegen testcases for 32-bit subregister support

2018-02-23 23:49:33 +00:00

Generic

[DebugInfo] Add remaining files to r325970

2018-02-23 23:13:18 +00:00

Hexagon

[Hexagon] Recognize non-immediate constants in HexagonConstPropagation

2018-02-23 20:33:26 +00:00

Inputs

…

Lanai

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

[MIPS GlobalISel] Adding GlobalISel

2018-02-23 11:06:40 +00:00

MIR

[GISel]: Verify COPIES involving generic registers.

2018-02-09 01:27:23 +00:00

MSP430

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (load)))->(and (zextload)) even when the and does not have multiple uses

2018-02-15 20:20:32 +00:00

PowerPC

[PowerPC] Disable shrink-wrapping when getting PC address through the LR

2018-02-23 23:08:34 +00:00

RISCV

[RISCV] Revert r324172 now r323991 was reverted

2018-02-17 18:17:47 +00:00

SPARC

[Sparc] Include __tls_get_addr in symbol table for TLS calls to it

2018-02-21 15:25:26 +00:00

SystemZ

[SystemZ] Also update the CHECK line for VPDI

2018-02-23 13:22:46 +00:00

Thumb

[ARM] Fix issue with large xor constants.

2018-02-22 09:38:57 +00:00

Thumb2

[ARM] Return true in enableMultipleCopyHints().

2018-02-16 09:51:01 +00:00

WebAssembly

[WebAssembly] Add mechanisms for specifying an explicit import module name.

2018-02-09 23:13:22 +00:00

WinCFGuard

Reland "Emit Function IDs table for Control Flow Guard"

2018-01-09 23:49:30 +00:00

WinEH

…

X86

[X86] Remove checks for '(scalar_to_vector (i8 (trunc GR32:)))' from scalar masked move patterns.

2018-02-24 00:15:05 +00:00

XCore

Emit smaller exception tables for non-SJLJ mode.

2018-02-09 17:13:37 +00:00