Min-Yih Hsu 4cb8f97a09

[clang][RISCV] Add C intrinsics for XSfvfexp* and XSfvfexpa* (#165792) ...

Add C intrinsics for XSfvfexp16e/32e, XSfvfbfexp16e, and XSfvfexpa(64e)
introduced in #164349 and #164499

Co-authored-by: Jesse Huang <jesse.huang@sifive.com>
Co-authored-by: Craig Topper <craig.topper@sifive.com>

2025-11-03 09:04:04 -08:00

..

andes-intrinsics

[RISCV] Implement intrinsics for XAndesVSIntLoad (#147767)

2025-07-10 09:11:29 +08:00

ntlh-intrinsics

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rvb-intrinsics

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rvk-intrinsics

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rvv-intrinsics-autogenerated

[RISCV][clang] Support Zvfbfa C intrinsics (#164094)

2025-10-18 23:24:16 +08:00

rvv-intrinsics-handcrafted

[RISCV] Make "target-feature +i" explicit (#157835)

2025-09-11 08:49:06 +02:00

rvv-intrinsics-sifive

[clang][RISCV] Add C intrinsics for XSfvfexp* and XSfvfexpa* (#165792)

2025-11-03 09:04:04 -08:00

sifive-intrinsics

[RISCV] Move intrinsic tests for Xsfvcp to sifive-intrinsics sub-directory. NFC.

2025-07-14 13:08:40 +08:00

__fp16-convert.c

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abi-empty-structs.c

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attr-hw-shadow-stack.c

[Clang][RISCV] Loosen the requirement of -fcf-protection=return to zimop (#152252)

2025-09-09 22:49:40 +08:00

attr-riscv-rvv-vector-bits-less-8-call.c

[RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (#139190)

2025-05-14 10:27:00 -07:00

attr-riscv-rvv-vector-bits-less-8-cast.c

[RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (#139190)

2025-05-14 10:27:00 -07:00

attr-rvv-vector-bits-bitcast-less-8.c

[clang][CodeGen] Emit llvm.tbaa.errno metadata during module creation

2025-10-21 11:38:45 +02:00

attr-rvv-vector-bits-bitcast.c

[clang][CodeGen] Emit llvm.tbaa.errno metadata during module creation

2025-10-21 11:38:45 +02:00

attr-rvv-vector-bits-call.c

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attr-rvv-vector-bits-cast.c

[clang][CodeGen] Emit llvm.tbaa.errno metadata during module creation

2025-10-21 11:38:45 +02:00

attr-rvv-vector-bits-codegen.c

[RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (#139190)

2025-05-14 10:27:00 -07:00

attr-rvv-vector-bits-globals.c

[clang][CodeGen] Emit llvm.tbaa.errno metadata during module creation

2025-10-21 11:38:45 +02:00

attr-rvv-vector-bits-types.c

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bfloat-abi.c

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bfloat-mangle.cpp

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bitint.c

[clang][RISCV] support BITINT with mixed-type (#156592)

2025-10-14 15:57:35 +08:00

builtin-cpu-is-error.c

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builtin-cpu-is.c

[RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550. (#159465)

2025-09-18 07:16:51 -07:00

builtins-riscv-mips.c

RISC-V: builtins support for MIPS RV64 P8700 execution control .

2025-09-19 15:10:28 +05:30

Float16-arith.c

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fpconstrained.c

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issue-129995.cpp

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math-builtins.c

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riscv32-abi.c

[clang][CodeGen] Set dead_on_return when passing arguments indirectly

2025-07-18 11:50:18 +02:00

riscv32-ilp32d-abi.cpp

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riscv32-ilp32e-error.c

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riscv32-int128-abi.c

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riscv32-vararg.c

[clang][CodeGen] Set dead_on_return when passing arguments indirectly

2025-07-18 11:50:18 +02:00

riscv64-abi.c

[clang][CodeGen] Set dead_on_return when passing arguments indirectly

2025-07-18 11:50:18 +02:00

riscv64-vararg.c

[clang][CodeGen] Set dead_on_return when passing arguments indirectly

2025-07-18 11:50:18 +02:00

riscv-abi.cpp

[clang][CodeGen] Set dead_on_return when passing arguments indirectly

2025-07-18 11:50:18 +02:00

riscv-atomics.c

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riscv-attr-builtin-alias-err.c

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riscv-attr-builtin-alias.c

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riscv-cf-protection.c

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riscv-func-attr-target-err.c

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riscv-func-attr-target.c

[RISCV] Make "target-feature +i" explicit (#157835)

2025-09-11 08:49:06 +02:00

riscv-inline-asm-clobber.c

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riscv-inline-asm-fixed-length-vector.c

[RISCV][llvm] Support fixed-length vector inline assembly constraints (#150724)

2025-08-18 03:36:12 +00:00

riscv-inline-asm-rvv.c

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riscv-inline-asm.c

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riscv-metadata-arch.c

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riscv-metadata.c

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riscv-sdata-module-flag.c

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riscv-v-lifetime.cpp

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

riscv-vector-callingconv-llvm-ir.c

[clang][RISCV] Fix crash on VLS calling convention (#145489)

2025-08-20 16:39:02 +08:00

riscv-vector-callingconv-llvm-ir.cpp

[clang][RISCV] Fix crash on VLS calling convention (#145489)

2025-08-20 16:39:02 +08:00

riscv-vector-callingconv.c

[Clang] include attribute scope in diagnostics (#144619)

2025-07-08 11:36:52 +03:00

riscv-vector-callingconv.cpp

[Clang] include attribute scope in diagnostics (#144619)

2025-07-08 11:36:52 +03:00

riscv-xandesbfhcvt-c-api.c

[RISCV] Implement Builtins for XAndesBFHCvt extension. (#148804)

2025-07-16 16:13:31 +08:00

riscv-xandesbfhcvt.c

[RISCV] Implement Builtins for XAndesBFHCvt extension. (#148804)

2025-07-16 16:13:31 +08:00

riscv-xcvalu-c-api.c

[RISCV] Run mem2reg for riscv-xcvalu-c-api.c and riscv-xcvalu.c. NFC.

2025-07-08 11:04:10 +08:00

riscv-xcvalu.c

[RISCV] Run mem2reg for riscv-xcvalu-c-api.c and riscv-xcvalu.c. NFC.

2025-07-08 11:04:10 +08:00

riscv-zihintpause.c

[RISCV] Add zihintpause LLVM/Clang intrinsic (#139519)

2025-05-16 14:20:53 +08:00

rvv-vls-arith-ops.c

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rvv-vls-bitwise-ops.c

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rvv-vls-compare-ops.c

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rvv-vls-shift-ops.c

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rvv-vls-subscript-ops.c

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tls-dialect.c

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vector-bits-vscale-range.c

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