579 lines
22 KiB
TableGen
579 lines
22 KiB
TableGen
//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions introduced for the Future CPU.
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//
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//===----------------------------------------------------------------------===//
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class XForm_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern> : I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<5> RS;
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let Pattern = pattern;
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let Inst{6...10} = RS;
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let Inst{11...20} = 0;
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let Inst{21...30} = xo;
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let Inst{31} = 0;
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}
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class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<5> RT;
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bits<5> RA;
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bits<5> RB;
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bit L;
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let Pattern = pattern;
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bit RC = 0; // set by isRecordForm
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let Inst{6...10} = RT;
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let Inst{11...15} = RA;
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let Inst{16...20} = RB;
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let Inst{21} = L;
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let Inst{22...30} = xo;
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let Inst{31} = RC;
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}
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multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmbase, string asmstr, list<dag> pattern> {
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let BaseName = asmbase in {
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def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(" ", asmstr)),
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pattern>,
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RecFormRel;
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let Defs = [CR0] in def _rec
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: XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(". ", asmstr)), []>,
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isRecordForm, RecFormRel;
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}
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}
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class VXForm_VRTB5_Base<bits<11> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<4, OOL, IOL, asmstr, NoItinerary> {
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bits<5> VRT;
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bits<5> VRB;
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let Pattern = pattern;
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let Inst{6...10} = VRT;
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let Inst{16...20} = VRB;
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let Inst{21...31} = xo;
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}
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class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
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let Inst{11...15} = R;
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}
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class VXForm_VRTB5_UIM2<bits<11> xo, bits<3> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
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bits<2> UIM;
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let Inst{11...13} = R;
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let Inst{14...15} = UIM;
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}
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class VXForm_VRTB5_UIM1<bits<11> xo, bits<4> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
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bits<1> UIM;
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let Inst{11...14} = R;
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let Inst{15} = UIM;
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}
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class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
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bits<3> UIM;
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let Inst{11...12} = R;
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let Inst{13...15} = UIM;
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}
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class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: VXForm_VRTB5_Base<xo, OOL, IOL, asmstr, pattern> {
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bits<5> VRA;
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let Inst{11...15} = VRA;
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}
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class XX3Form_XTBp5_M2<bits<9> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<60, OOL, IOL, asmstr, NoItinerary> {
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bits<5> XTp;
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bits<5> XBp;
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bits<2> M;
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let Pattern = pattern;
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let Inst{6...9} = XTp{3...0};
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let Inst {10} = XTp{4};
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let Inst{15} = M{0};
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let Inst{16...19} = XBp{3...0};
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let Inst{20} = M{1};
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let Inst{21...29} = xo;
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let Inst{30} = XBp{4};
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}
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class XX3Form_XTABp5_M2<bits<8> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<60, OOL, IOL, asmstr, NoItinerary> {
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bits<5> XTp;
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bits<5> XAp;
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bits<5> XBp;
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bits<2> M;
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let Pattern = pattern;
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let Inst{6...9} = XTp{3...0};
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let Inst{10} = XTp{4};
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let Inst{11...14} = XAp{3...0};
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let Inst{15} = M{0};
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let Inst{16...19} = XBp{3...0};
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let Inst{20} = M{1};
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let Inst{21...28} = xo;
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let Inst{29} = XAp{4};
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let Inst{30} = XBp{4};
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}
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class XX3Form_XTAB6_P1<bits<5> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<60, OOL, IOL, asmstr, NoItinerary> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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bits<1> P;
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let Pattern = pattern;
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let Inst{6...10} = XT{4...0};
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let Inst{11...15} = XA{4...0};
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let Inst{16...20} = XB{4...0};
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let Inst{21...22} = 3;
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let Inst{23} = P;
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let Inst{24...28} = xo;
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let Inst{29} = XA{5};
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let Inst{30} = XB{5};
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let Inst{31} = XT{5};
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}
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class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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let Pattern = pattern;
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let Inst{6...10} = XT{4...0};
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let Inst{11...15} = XA{4...0};
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let Inst{16...20} = XB{4...0};
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let Inst{21...28} = xo;
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let Inst{29} = XA{5};
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let Inst{30} = XB{5};
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let Inst{31} = XT{5};
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}
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class XForm_RBS5<bits<6> opCode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opCode, OOL, IOL, asmstr, itin> {
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bits<5> RB;
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bits<5> RS;
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let Pattern = pattern;
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let Inst{6...10} = RS;
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let Inst{11...15} = 0;
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let Inst{16...20} = RB;
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let Inst{21...30} = xo;
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let Inst{31} = 0;
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}
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class XX3Form_XTAB6_S<bits<5> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<59, OOL, IOL, asmstr, NoItinerary> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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let Pattern = pattern;
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let Inst{6...10} = XT{4...0};
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let Inst{11...15} = XA{4...0};
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let Inst{16...20} = XB{4...0};
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let Inst{24...28} = xo;
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let Inst{29} = XA{5};
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let Inst{30} = XB{5};
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let Inst{31} = XT{5};
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}
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class XX3Form_XTAB6_S3<bits<5> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {
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bits<3> S;
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let Inst{21...23} = S;
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}
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class XX3Form_XTAB6_3S1<bits<5> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {
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bits<1> S0;
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bits<1> S1;
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bits<1> S2;
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let Inst{21} = S0;
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let Inst{22} = S1;
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let Inst{23} = S2;
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}
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class XX3Form_XTAB6_2S1<bits<5> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: XX3Form_XTAB6_S<xo, OOL, IOL, asmstr, pattern> {
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bits<1> S1;
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bits<1> S2;
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let Inst{21} = 0;
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let Inst{22} = S1;
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let Inst{23} = S2;
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}
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class XX3Form_XTAB6_P<bits<7> xo, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: I<59, OOL, IOL, asmstr, NoItinerary> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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bits<1> P;
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let Pattern = pattern;
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let Inst{6...10} = XT{4...0};
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let Inst{11...15} = XA{4...0};
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let Inst{16...20} = XB{4...0};
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let Inst{21} = P;
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let Inst{22...28} = xo;
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let Inst{29} = XA{5};
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let Inst{30} = XB{5};
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let Inst{31} = XT{5};
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}
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// Prefix instruction classes.
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class 8RR_XX4Form_XTABC6_P<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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bits<6> XC;
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bits<1> P;
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let Pattern = pattern;
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// The prefix.
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let Inst{6...7} = 1;
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let Inst{8...11} = 0;
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// The instruction.
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let Inst{38...42} = XT{4...0};
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let Inst{43...47} = XA{4...0};
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let Inst{48...52} = XB{4...0};
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let Inst{53...57} = XC{4...0};
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let Inst{58} = 1;
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let Inst{59} = P;
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let Inst{60} = XC{5};
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let Inst{61} = XA{5};
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let Inst{62} = XB{5};
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let Inst{63} = XT{5};
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}
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//-------------------------- Instruction definitions -------------------------//
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// Predicate combinations available:
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// [IsISAFuture]
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// [HasVSX, IsISAFuture]
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// [HasVSX, PrefixInstrs, IsISAFuture]
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let Predicates = [IsISAFuture] in {
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defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
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(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
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"$RT, $L, $RA, $RB", []>;
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def TLBSYNCIO
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: XForm_RS5<31, 564, (outs), (ins g8rc:$RS), "tlbsyncio $RS", []>;
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def PTESYNCIO
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: XForm_RS5<31, 596, (outs), (ins g8rc:$RS), "ptesyncio $RS", []>;
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def TLBIEP : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
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(ins gprc:$RB, gprc:$RS, u2imm:$RIC,
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u1imm:$PRS, u1imm:$R),
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"tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
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def TLBIEIO
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: XForm_RSB5_UIMM2<31, 18, (outs), (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC),
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"tlbieio $RB, $RS, $RIC", []>;
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def MTLPL : XForm_RBS5<31, 275, (outs), (ins gprc:$RB, gprc:$RS),
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"mtlpl $RB, $RS", IIC_SprMTSPR, []>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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def TLBIEP8
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: XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
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(ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
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u1imm:$PRS, u1imm:$R),
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"tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
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def MTLPL8 : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),
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"mtlpl $RB, $RS", IIC_SprMTSPR, []>, isPPC64;
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}
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}
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let Predicates = [HasVSX, IsISAFuture] in {
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let mayLoad = 1 in {
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def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
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def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
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def LXVPRL : XForm_XTp5_RAB5<31, 589, (outs vsrprc:$XTp),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
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def LXVPRLL : XForm_XTp5_RAB5<31, 621, (outs vsrprc:$XTp),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
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def LXVPB32X
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: XForm_XTp5_RAB5<31, 877, (outs vsrprc:$XTp),
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(ins (memr $RA):$addr, g8rc:$RB),
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"lxvpb32x $XTp, $addr, $RB", IIC_LdStLFD, []>;
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}
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let mayStore = 1 in {
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def STXVRL : XX1Form_memOp<31, 653, (outs),
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(ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
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"stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
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def STXVRLL : XX1Form_memOp<31, 685, (outs),
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(ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
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"stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
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def STXVPRL : XForm_XTp5_RAB5<31, 717, (outs),
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(ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
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"stxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
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def STXVPRLL
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: XForm_XTp5_RAB5<31, 749, (outs),
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(ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
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"stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
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def STXVPB32X
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: XForm_XTp5_RAB5<31, 1005, (outs),
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(ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
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"stxvpb32x $XTp, $addr, $RB", IIC_LdStLFD, []>;
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}
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def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB),
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"vupkhsntob $VRT, $VRB", []>;
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def VUPKLSNTOB : VXForm_VRTB5<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB),
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"vupklsntob $VRT, $VRB", []>;
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def VUPKINT4TOBF16
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: VXForm_VRTB5_UIM2<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
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"vupkint4tobf16 $VRT, $VRB, $UIM", []>;
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def VUPKINT8TOBF16
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: VXForm_VRTB5_UIM1<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB, u1imm:$UIM),
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"vupkint8tobf16 $VRT, $VRB, $UIM", []>;
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def VUPKINT8TOFP32
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: VXForm_VRTB5_UIM2<387, 3, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
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"vupkint8tofp32 $VRT, $VRB, $UIM", []>;
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def VUPKINT4TOFP32
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: VXForm_VRTB5_UIM3<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u3imm:$UIM),
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"vupkint4tofp32 $VRT, $VRB, $UIM", []>;
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def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprhn $VRT, $VRA, $VRB", []>;
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def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprln $VRT, $VRA, $VRB", []>;
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def VUCMPRHB
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: VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprhb $VRT, $VRA, $VRB", []>;
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def VUCMPRLB
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: VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprlb $VRT, $VRA, $VRB", []>;
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def VUCMPRHH
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: VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
|
|
"vucmprhh $VRT, $VRA, $VRB", []>;
|
|
def VUCMPRLH
|
|
: VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
|
|
"vucmprlh $VRT, $VRA, $VRB", []>;
|
|
|
|
// AES Acceleration Instructions
|
|
def XXAESENCP : XX3Form_XTABp5_M2<194, (outs vsrprc:$XTp),
|
|
(ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),
|
|
"xxaesencp $XTp, $XAp, $XBp, $M", []>;
|
|
def XXAESDECP : XX3Form_XTABp5_M2<202, (outs vsrprc:$XTp),
|
|
(ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),
|
|
"xxaesdecp $XTp, $XAp, $XBp, $M", []>;
|
|
def XXAESGENLKP : XX3Form_XTBp5_M2<420, (outs vsrprc:$XTp),
|
|
(ins vsrprc:$XBp, u2imm:$M),
|
|
"xxaesgenlkp $XTp, $XBp, $M", []>;
|
|
def XXGFMUL128 : XX3Form_XTAB6_P1<26, (outs vsrc:$XT),
|
|
(ins vsrc:$XA, vsrc:$XB, u1imm:$P),
|
|
"xxgfmul128 $XT, $XA, $XB, $P", []>;
|
|
|
|
// VSX Vector Integer Arithmetic Instructions
|
|
def XVADDUWM : XX3Form_XTAB6<60, 131, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvadduwm $XT, $XA, $XB", []>;
|
|
def XVADDUHM : XX3Form_XTAB6<60, 139, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvadduhm $XT, $XA, $XB", []>;
|
|
def XVSUBUWM: XX3Form_XTAB6<60, 147, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvsubuwm $XT, $XA, $XB", []>;
|
|
def XVSUBUHM: XX3Form_XTAB6<60, 155, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvsubuhm $XT, $XA, $XB", []>;
|
|
def XVMULUWM: XX3Form_XTAB6<60, 163, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmuluwm $XT, $XA, $XB", []>;
|
|
def XVMULUHM: XX3Form_XTAB6<60, 171, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmuluhm $XT, $XA, $XB", []>;
|
|
def XVMULHSW: XX3Form_XTAB6<60, 179, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmulhsw $XT, $XA, $XB", []>;
|
|
def XVMULHSH: XX3Form_XTAB6<60, 187, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmulhsh $XT, $XA, $XB", []>;
|
|
def XVMULHUW: XX3Form_XTAB6<60, 114, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmulhuw $XT, $XA, $XB", []>;
|
|
def XVMULHUH: XX3Form_XTAB6<60, 122, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xvmulhuh $XT, $XA, $XB", []>;
|
|
|
|
// Elliptic Curve Cryptography Acceleration Instructions.
|
|
def XXMULMUL
|
|
: XX3Form_XTAB6_S3<1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u3imm:$S),
|
|
"xxmulmul $XT, $XA, $XB, $S", []>;
|
|
def XXMULMULHIADD
|
|
: XX3Form_XTAB6_3S1<9, (outs vsrc:$XT),
|
|
(ins vsrc:$XA, vsrc:$XB, u1imm:$S0, u1imm:$S1,
|
|
u1imm:$S2),
|
|
"xxmulmulhiadd $XT, $XA, $XB, $S0, $S1, $S2", []>;
|
|
def XXMULMULLOADD
|
|
: XX3Form_XTAB6_2S1<17, (outs vsrc:$XT),
|
|
(ins vsrc:$XA, vsrc:$XB, u1imm:$S1, u1imm:$S2),
|
|
"xxmulmulloadd $XT, $XA, $XB, $S1, $S2", []>;
|
|
def XXSSUMUDM
|
|
: XX3Form_XTAB6_P<25, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u1imm:$P),
|
|
"xxssumudm $XT, $XA, $XB, $P", []>;
|
|
def XXSSUMUDMC
|
|
: XX3Form_XTAB6_P<57, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u1imm:$P),
|
|
"xxssumudmc $XT, $XA, $XB, $P", []>;
|
|
def XSADDADDUQM
|
|
: XX3Form_XTAB6<59, 96, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsaddadduqm $XT, $XA, $XB", []>;
|
|
def XSADDADDSUQM
|
|
: XX3Form_XTAB6<59, 104, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsaddaddsuqm $XT, $XA, $XB", []>;
|
|
def XSADDSUBUQM
|
|
: XX3Form_XTAB6<59, 112, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsaddsubuqm $XT, $XA, $XB", []>;
|
|
def XSADDSUBSUQM
|
|
: XX3Form_XTAB6<59, 224, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsaddsubsuqm $XT, $XA, $XB", []>;
|
|
def XSMERGE2T1UQM
|
|
: XX3Form_XTAB6<59, 232, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsmerge2t1uqm $XT, $XA, $XB", []>;
|
|
def XSMERGE2T2UQM
|
|
: XX3Form_XTAB6<59, 240, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsmerge2t2uqm $XT, $XA, $XB", []>;
|
|
def XSMERGE2T3UQM
|
|
: XX3Form_XTAB6<59, 89, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsmerge2t3uqm $XT, $XA, $XB", []>;
|
|
def XSMERGE3T1UQM
|
|
: XX3Form_XTAB6<59, 121, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsmerge3t1uqm $XT, $XA, $XB", []>;
|
|
def XSREBASE2T1UQM
|
|
: XX3Form_XTAB6<59, 145, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsrebase2t1uqm $XT, $XA, $XB", []>;
|
|
def XSREBASE2T2UQM
|
|
: XX3Form_XTAB6<59, 177, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsrebase2t2uqm $XT, $XA, $XB", []>;
|
|
def XSREBASE2T3UQM
|
|
: XX3Form_XTAB6<59, 209, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsrebase2t3uqm $XT, $XA, $XB", []>;
|
|
def XSREBASE2T4UQM
|
|
: XX3Form_XTAB6<59, 217, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsrebase2t4uqm $XT, $XA, $XB", []>;
|
|
def XSREBASE3T1UQM
|
|
: XX3Form_XTAB6<59, 241, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsrebase3t1uqm $XT, $XA, $XB", []>;
|
|
def XSREBASE3T2UQM
|
|
: XX3Form_XTAB6<59, 249, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsrebase3t2uqm $XT, $XA, $XB", []>;
|
|
def XSREBASE3T3UQM
|
|
: XX3Form_XTAB6<59, 195, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
|
|
"xsrebase3t3uqm $XT, $XA, $XB", []>;
|
|
}
|
|
|
|
let Predicates = [HasVSX, PrefixInstrs, IsISAFuture] in {
|
|
def XXSSUMUDMCEXT
|
|
: 8RR_XX4Form_XTABC6_P<
|
|
34, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC, u1imm:$P),
|
|
"xxssumudmcext $XT, $XA, $XB, $XC, $P", IIC_VecGeneral, []>;
|
|
}
|
|
|
|
//---------------------------- Anonymous Patterns ----------------------------//
|
|
// Predicate combinations available:
|
|
|
|
// Load/Store VSX Vector with Right Length (Left-justified).
|
|
def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
|
|
def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
|
|
def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
|
|
$RB)>;
|
|
def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
|
|
$RB)>;
|
|
|
|
// Load/Store VSX Vector pair with Right Length (Left-justified).
|
|
def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
|
|
def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
|
|
def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
|
|
$RA, $RB)>;
|
|
def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
|
|
$RA, $RB)>;
|
|
|
|
//---------------------------- Instruction aliases ---------------------------//
|
|
// Predicate combinations available:
|
|
// [HasVSX, IsISAFuture]
|
|
|
|
let Predicates = [HasVSX, IsISAFuture] in {
|
|
def : InstAlias<"xxaes128encp $XTp, $XAp, $XBp",
|
|
(XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;
|
|
def : InstAlias<"xxaes192encp $XTp, $XAp, $XBp",
|
|
(XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;
|
|
def : InstAlias<"xxaes256encp $XTp, $XAp, $XBp",
|
|
(XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;
|
|
def : InstAlias<"xxaes128decp $XTp, $XAp, $XBp",
|
|
(XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;
|
|
def : InstAlias<"xxaes192decp $XTp, $XAp, $XBp",
|
|
(XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;
|
|
def : InstAlias<"xxaes256decp $XTp, $XAp, $XBp",
|
|
(XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;
|
|
def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
|
|
vsrprc:$XBp, 0)>;
|
|
def : InstAlias<"xxaes192genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
|
|
vsrprc:$XBp, 1)>;
|
|
def : InstAlias<"xxaes256genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
|
|
vsrprc:$XBp, 2)>;
|
|
def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,
|
|
vsrc:$XB, 0)>;
|
|
def : InstAlias<"xxgfmul128xts $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,
|
|
vsrc:$XB, 1)>;
|
|
}
|