98727f6a8f
In binary form, 64-bit values are split into two 32-bit values as per the spec. Naturally this works fine with all tools. However, the text format does not have a formal specification but SPIR-V-Tools, which we already rely on in the SPIRV workflow (clang calls `spirv-as` for example), expects the full 64 bit value, but today we print the two 32-bit values. causing the tool to error and report that the format is invalid. The SPIR-V Translator also prints a single 64-bit value for text format. This case is already handled specifically for `OpConstant`, but `OpSwitch` was missed. The SPIR-V translator also has special code in `OpSwitch` handling for this case. Recombine the two 32-bit operands into a single 64-bit value to print in `AsmPrinter`. The actual ASM (aka binary form) emission is unchanged. --------- Signed-off-by: Sarnie, Nick <nick.sarnie@intel.com>
75 lines
2.7 KiB
C++
75 lines
2.7 KiB
C++
//=- SPIRVMCInstLower.cpp - Convert SPIR-V MachineInstr to MCInst -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower SPIR-V MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVMCInstLower.h"
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#include "SPIRVModuleAnalysis.h"
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#include "SPIRVUtils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Constants.h"
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using namespace llvm;
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void SPIRVMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI,
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SPIRV::ModuleAnalysisInfo *MAI) const {
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OutMI.setOpcode(MI->getOpcode());
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// Propagate previously set flags
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if (MI->getAsmPrinterFlags() & SPIRV::ASM_PRINTER_WIDTH16)
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OutMI.setFlags(SPIRV::INST_PRINTER_WIDTH16);
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if (MI->getAsmPrinterFlags() & SPIRV::ASM_PRINTER_WIDTH64)
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OutMI.setFlags(SPIRV::INST_PRINTER_WIDTH64);
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const MachineFunction *MF = MI->getMF();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_GlobalAddress: {
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MCRegister FuncReg = MAI->getFuncReg(dyn_cast<Function>(MO.getGlobal()));
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if (!FuncReg.isValid()) {
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std::string DiagMsg;
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raw_string_ostream OS(DiagMsg);
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MI->print(OS);
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DiagMsg = "Unknown function in:" + DiagMsg;
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report_fatal_error(DiagMsg.c_str());
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}
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MCOp = MCOperand::createReg(FuncReg);
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::createReg(MAI->getOrCreateMBBRegister(*MO.getMBB()));
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break;
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case MachineOperand::MO_Register: {
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MCRegister NewReg = MAI->getRegisterAlias(MF, MO.getReg());
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MCOp = MCOperand::createReg(NewReg.isValid() ? NewReg
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: MO.getReg().asMCReg());
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break;
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}
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case MachineOperand::MO_Immediate:
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if (MI->getOpcode() == SPIRV::OpExtInst && i == 2) {
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MCRegister Reg = MAI->getExtInstSetReg(MO.getImm());
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MCOp = MCOperand::createReg(Reg);
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} else {
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MCOp = MCOperand::createImm(MO.getImm());
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}
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break;
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case MachineOperand::MO_FPImmediate:
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MCOp = MCOperand::createDFPImm(
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MO.getFPImm()->getValueAPF().convertToFloat());
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break;
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}
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OutMI.addOperand(MCOp);
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}
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}
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