125f0ac757
As shown in #137101, fp16 lrint are not handled correctly on Arm. This adds soft-half promotion for them, reusing the function that promotes a value with operands (and can handle strict fp once that is added).
81 lines
2.7 KiB
LLVM
81 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
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; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
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; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8
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; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
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define i64 @testmsxh_builtin(half %x) {
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; CHECK-SOFT-LABEL: testmsxh_builtin:
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; CHECK-SOFT: @ %bb.0: @ %entry
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; CHECK-SOFT-NEXT: .save {r11, lr}
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; CHECK-SOFT-NEXT: push {r11, lr}
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; CHECK-SOFT-NEXT: bl __aeabi_h2f
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; CHECK-SOFT-NEXT: bl llrintf
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; CHECK-SOFT-NEXT: pop {r11, pc}
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;
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; CHECK-NOFP16-LABEL: testmsxh_builtin:
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; CHECK-NOFP16: @ %bb.0: @ %entry
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; CHECK-NOFP16-NEXT: .save {r11, lr}
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; CHECK-NOFP16-NEXT: push {r11, lr}
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; CHECK-NOFP16-NEXT: vmov r0, s0
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; CHECK-NOFP16-NEXT: bl __aeabi_h2f
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; CHECK-NOFP16-NEXT: vmov s0, r0
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; CHECK-NOFP16-NEXT: bl llrintf
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; CHECK-NOFP16-NEXT: pop {r11, pc}
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;
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; CHECK-FPv8-LABEL: testmsxh_builtin:
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; CHECK-FPv8: @ %bb.0: @ %entry
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; CHECK-FPv8-NEXT: .save {r11, lr}
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; CHECK-FPv8-NEXT: push {r11, lr}
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; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0
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; CHECK-FPv8-NEXT: bl llrintf
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; CHECK-FPv8-NEXT: pop {r11, pc}
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;
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; CHECK-FP16-LABEL: testmsxh_builtin:
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; CHECK-FP16: @ %bb.0: @ %entry
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; CHECK-FP16-NEXT: .save {r11, lr}
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; CHECK-FP16-NEXT: push {r11, lr}
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; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0
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; CHECK-FP16-NEXT: bl llrintf
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; CHECK-FP16-NEXT: pop {r11, pc}
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
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ret i64 %0
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}
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define i64 @testmsxs_builtin(float %x) {
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; CHECK-LABEL: testmsxs_builtin:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: bl llrintf
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; CHECK-NEXT: pop {r11, pc}
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f32(float %x)
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ret i64 %0
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}
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define i64 @testmsxd_builtin(double %x) {
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; CHECK-LABEL: testmsxd_builtin:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: bl llrint
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; CHECK-NEXT: pop {r11, pc}
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f64(double %x)
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ret i64 %0
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}
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define i64 @testmsxq_builtin(fp128 %x) {
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; CHECK-LABEL: testmsxq_builtin:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: bl llrintl
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; CHECK-NEXT: pop {r11, pc}
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f128(fp128 %x)
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ret i64 %0
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}
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