42ab473f51
This change implements support for the combination of Xqci and the Short Forward Branch optimisation. In particular, we want to prioritise `Branch+ALU` (short forward branches) over the equivalent `ALU+CMov`, when the compared values are both registers, and the selected values come from registers (as this is what `PseudoCCMOVGPR` supports). However, when expanding `PseudoCCMOVGPR` (i.e., `Branch+MV`), we instead want to expand it to a conditional move (for code size reasons), so I have added `RISCVExpandPseudo::expandCCOpToCMov` to try to do so. This mostly works, except if `PseudoCCMOVGPR` is comparing against zero and gets commuted - as can be seen in one example in `foo` in `select-cc.ll`. This change: - updates the attributes used for the XQCI RUN lines for the select tests. - modifies the CodeGen patterns and predicates to prioritise selecting the SFB Pseudo. - adds CodeGen patterns for MVLTI/MVLTUI/MVGEI/MVGEUI with imm=zero, to prioritise over the equivalent `Select_GPR_Using_CC_GPR` patterns for rhs=X0. - adds a hook to attempt to turn the predicated-mov Pseudo back into a Conditional Move from Xqcicm (which matches the pseudo in terms of tied register operands).
62 lines
2.0 KiB
LLVM
62 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
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define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
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; RV32I-LABEL: bare_select:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a3, a0, 1
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: bnez a3, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: ret
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;
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; RV64I-CCMOV-LABEL: bare_select:
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; RV64I-CCMOV: # %bb.0:
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; RV64I-CCMOV-NEXT: andi a0, a0, 1
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; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2
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; RV64I-CCMOV-NEXT: ret
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;
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; RV32IXQCI-LABEL: bare_select:
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; RV32IXQCI: # %bb.0:
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; RV32IXQCI-NEXT: andi a0, a0, 1
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; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
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; RV32IXQCI-NEXT: mv a0, a1
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; RV32IXQCI-NEXT: ret
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%1 = select i1 %a, i32 %b, i32 %c
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ret i32 %1
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}
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define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
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; RV32I-LABEL: bare_select_float:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a3, a0, 1
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: bnez a3, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: ret
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;
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; RV64I-CCMOV-LABEL: bare_select_float:
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; RV64I-CCMOV: # %bb.0:
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; RV64I-CCMOV-NEXT: andi a0, a0, 1
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; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2
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; RV64I-CCMOV-NEXT: ret
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;
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; RV32IXQCI-LABEL: bare_select_float:
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; RV32IXQCI: # %bb.0:
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; RV32IXQCI-NEXT: andi a0, a0, 1
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; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
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; RV32IXQCI-NEXT: mv a0, a1
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; RV32IXQCI-NEXT: ret
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%1 = select i1 %a, float %b, float %c
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ret float %1
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}
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