shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/RISCV/select-const.ll
Sam Elliott 42ab473f51
[RISCV] Xqci with Short Forward Branches (#161407) 
This change implements support for the combination of Xqci and the Short
Forward Branch optimisation.

In particular, we want to prioritise `Branch+ALU` (short forward
branches) over the equivalent `ALU+CMov`, when the compared values are
both registers, and the selected values come from registers (as this is
what `PseudoCCMOVGPR` supports).

However, when expanding `PseudoCCMOVGPR` (i.e., `Branch+MV`), we instead
want to expand it to a conditional move (for code size reasons), so I
have added `RISCVExpandPseudo::expandCCOpToCMov` to try to do so. This
mostly works, except if `PseudoCCMOVGPR` is comparing against zero and
gets commuted - as can be seen in one example in `foo` in
`select-cc.ll`.

This change:
- updates the attributes used for the XQCI RUN lines for the select
tests.
- modifies the CodeGen patterns and predicates to prioritise selecting
the SFB Pseudo.
- adds CodeGen patterns for MVLTI/MVLTUI/MVGEI/MVGEUI with imm=zero, to
prioritise over the equivalent `Select_GPR_Using_CC_GPR` patterns for
rhs=X0.
- adds a hook to attempt to turn the predicated-mov Pseudo back into a
Conditional Move from Xqcicm (which matches the pseudo in terms of tied
register operands).
2025-10-01 10:00:40 -07:00

1424 lines
39 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+zicond -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+zicond -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64ZICOND %s
;; This tests how good we are at materialising constants using `select`. The aim
;; is that we do so without a branch if possible (at the moment our lowering of
;; select always introduces a branch).
;;
;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the
;; constants are either 1 away from each other, or one is a power of two and
;; the other is zero.
define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
; RV32-LABEL: select_const_int_easy:
; RV32: # %bb.0:
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_const_int_easy:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_const_int_easy:
; RV64: # %bb.0:
; RV64-NEXT: ret
%1 = select i1 %a, i32 1, i32 0
ret i32 %1
}
define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
; RV32-LABEL: select_const_int_one_away:
; RV32: # %bb.0:
; RV32-NEXT: li a1, 4
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_const_int_one_away:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, 4
; RV32IXQCI-NEXT: sub a0, a1, a0
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_const_int_one_away:
; RV64: # %bb.0:
; RV64-NEXT: li a1, 4
; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: ret
%1 = select i1 %a, i32 3, i32 4
ret i32 %1
}
define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
; RV32-LABEL: select_const_int_pow2_zero:
; RV32: # %bb.0:
; RV32-NEXT: slli a0, a0, 2
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_const_int_pow2_zero:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: slli a0, a0, 2
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_const_int_pow2_zero:
; RV64: # %bb.0:
; RV64-NEXT: slli a0, a0, 2
; RV64-NEXT: ret
%1 = select i1 %a, i32 4, i32 0
ret i32 %1
}
define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
; RV32I-LABEL: select_const_int_harder:
; RV32I: # %bb.0:
; RV32I-NEXT: bnez a0, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: li a0, 38
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: li a0, 6
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_const_int_harder:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bnez a0, .LBB3_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a0, 38
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: li a0, 6
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_const_int_harder:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: xori a0, a0, 1
; RV32ZICOND-NEXT: slli a0, a0, 5
; RV32ZICOND-NEXT: addi a0, a0, 6
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: select_const_int_harder:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, 38
; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 6
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_const_int_harder:
; RV64I: # %bb.0:
; RV64I-NEXT: bnez a0, .LBB3_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: li a0, 38
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: li a0, 6
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_const_int_harder:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bnez a0, .LBB3_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: li a0, 38
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB3_2:
; RV64IFD-NEXT: li a0, 6
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: select_const_int_harder:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: xori a0, a0, 1
; RV64ZICOND-NEXT: slli a0, a0, 5
; RV64ZICOND-NEXT: addiw a0, a0, 6
; RV64ZICOND-NEXT: ret
%1 = select i1 %a, i32 6, i32 38
ret i32 %1
}
define float @select_const_fp(i1 zeroext %a) nounwind {
; RV32I-LABEL: select_const_fp:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui a0, 263168
; RV32I-NEXT: bnez a1, .LBB4_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a0, 264192
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_const_fp:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bnez a0, .LBB4_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, 264192
; RV32IF-NEXT: j .LBB4_3
; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: lui a0, 263168
; RV32IF-NEXT: .LBB4_3:
; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fmv.x.w a0, fa5
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_const_fp:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: lui a1, 1024
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
; RV32ZICOND-NEXT: lui a1, 263168
; RV32ZICOND-NEXT: add a0, a0, a1
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: select_const_fp:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: lui a2, 263168
; RV32IXQCI-NEXT: lui a1, 264192
; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_const_fp:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui a0, 263168
; RV64I-NEXT: bnez a1, .LBB4_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 264192
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_const_fp:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bnez a0, .LBB4_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, 264192
; RV64IFD-NEXT: j .LBB4_3
; RV64IFD-NEXT: .LBB4_2:
; RV64IFD-NEXT: lui a0, 263168
; RV64IFD-NEXT: .LBB4_3:
; RV64IFD-NEXT: fmv.w.x fa5, a0
; RV64IFD-NEXT: fmv.x.w a0, fa5
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: select_const_fp:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: lui a1, 1024
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
; RV64ZICOND-NEXT: lui a1, 263168
; RV64ZICOND-NEXT: add a0, a0, a1
; RV64ZICOND-NEXT: ret
%1 = select i1 %a, float 3.0, float 4.0
ret float %1
}
define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_eq_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_eq_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a0, a0, a1
; RV32IXQCI-NEXT: snez a0, a0
; RV32IXQCI-NEXT: addi a0, a0, -1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_eq_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_ne_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_ne_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a0, a0, a1
; RV32IXQCI-NEXT: seqz a0, a0
; RV32IXQCI-NEXT: addi a0, a0, -1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_ne_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_sgt_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: slt a0, a1, a0
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_sgt_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: slt a0, a1, a0
; RV32IXQCI-NEXT: neg a0, a0
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_sgt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a1, a0
; RV64-NEXT: neg a0, a0
; RV64-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_slt_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: slt a0, a0, a1
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_slt_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: slt a0, a0, a1
; RV32IXQCI-NEXT: neg a0, a0
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_slt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a0, a1
; RV64-NEXT: neg a0, a0
; RV64-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_sge_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: slt a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_sge_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: slt a0, a0, a1
; RV32IXQCI-NEXT: addi a0, a0, -1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_sge_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_sle_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: slt a0, a1, a0
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_sle_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: slt a0, a1, a0
; RV32IXQCI-NEXT: addi a0, a0, -1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_sle_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: slt a0, a1, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_ugt_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: sltu a0, a1, a0
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_ugt_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: sltu a0, a1, a0
; RV32IXQCI-NEXT: neg a0, a0
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_ugt_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a1, a0
; RV64-NEXT: neg a0, a0
; RV64-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_ult_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_ult_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: sltu a0, a0, a1
; RV32IXQCI-NEXT: neg a0, a0
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_ult_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: neg a0, a0
; RV64-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_uge_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_uge_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: sltu a0, a0, a1
; RV32IXQCI-NEXT: addi a0, a0, -1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_uge_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32-LABEL: select_ule_zero_negone:
; RV32: # %bb.0:
; RV32-NEXT: sltu a0, a1, a0
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_ule_zero_negone:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: sltu a0, a1, a0
; RV32IXQCI-NEXT: addi a0, a0, -1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_ule_zero_negone:
; RV64: # %bb.0:
; RV64-NEXT: sltu a0, a1, a0
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define i32 @select_eq_1_2(i32 signext %a, i32 signext %b) {
; RV32-LABEL: select_eq_1_2:
; RV32: # %bb.0:
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_eq_1_2:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a0, a0, a1
; RV32IXQCI-NEXT: snez a0, a0
; RV32IXQCI-NEXT: addi a0, a0, 1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_eq_1_2:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, i32 1, i32 2
ret i32 %2
}
define i32 @select_ne_1_2(i32 signext %a, i32 signext %b) {
; RV32-LABEL: select_ne_1_2:
; RV32: # %bb.0:
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: addi a0, a0, 1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_ne_1_2:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a0, a0, a1
; RV32IXQCI-NEXT: seqz a0, a0
; RV32IXQCI-NEXT: addi a0, a0, 1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_ne_1_2:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, i32 1, i32 2
ret i32 %2
}
define i32 @select_eq_10000_10001(i32 signext %a, i32 signext %b) {
; RV32-LABEL: select_eq_10000_10001:
; RV32: # %bb.0:
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: lui a1, 2
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: addi a1, a1, 1810
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_eq_10000_10001:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a0, a0, a1
; RV32IXQCI-NEXT: lui a1, 2
; RV32IXQCI-NEXT: seqz a0, a0
; RV32IXQCI-NEXT: addi a1, a1, 1810
; RV32IXQCI-NEXT: sub a0, a1, a0
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_eq_10000_10001:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: lui a1, 2
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: addi a1, a1, 1810
; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, i32 10001, i32 10002
ret i32 %2
}
define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
; RV32-LABEL: select_ne_10001_10002:
; RV32: # %bb.0:
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: lui a1, 2
; RV32-NEXT: snez a0, a0
; RV32-NEXT: addi a1, a1, 1810
; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_ne_10001_10002:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: xor a0, a0, a1
; RV32IXQCI-NEXT: lui a1, 2
; RV32IXQCI-NEXT: snez a0, a0
; RV32IXQCI-NEXT: addi a1, a1, 1810
; RV32IXQCI-NEXT: sub a0, a1, a0
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_ne_10001_10002:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: lui a1, 2
; RV64-NEXT: snez a0, a0
; RV64-NEXT: addi a1, a1, 1810
; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, i32 10001, i32 10002
ret i32 %2
}
define i32 @select_slt_zero_constant1_constant2(i32 signext %x) {
; RV32-LABEL: select_slt_zero_constant1_constant2:
; RV32: # %bb.0:
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: andi a0, a0, 10
; RV32-NEXT: addi a0, a0, -3
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_slt_zero_constant1_constant2:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, -3
; RV32IXQCI-NEXT: qc.lilti a1, a0, 0, 7
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_slt_zero_constant1_constant2:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: andi a0, a0, 10
; RV64-NEXT: addi a0, a0, -3
; RV64-NEXT: ret
%cmp = icmp slt i32 %x, 0
%cond = select i1 %cmp, i32 7, i32 -3
ret i32 %cond
}
define i32 @select_sgt_negative_one_constant1_constant2(i32 signext %x) {
; RV32-LABEL: select_sgt_negative_one_constant1_constant2:
; RV32: # %bb.0:
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: andi a0, a0, -10
; RV32-NEXT: addi a0, a0, 7
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_sgt_negative_one_constant1_constant2:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, -3
; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 7
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_sgt_negative_one_constant1_constant2:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: andi a0, a0, -10
; RV64-NEXT: addi a0, a0, 7
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 7, i32 -3
ret i32 %cond
}
define i32 @select_nonnegative_lui_addi(i32 signext %x) {
; RV32I-LABEL: select_nonnegative_lui_addi:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui a0, 4
; RV32I-NEXT: bgez a1, .LBB21_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: li a0, 25
; RV32I-NEXT: .LBB21_2:
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_nonnegative_lui_addi:
; RV32IF: # %bb.0:
; RV32IF-NEXT: mv a1, a0
; RV32IF-NEXT: lui a0, 4
; RV32IF-NEXT: bgez a1, .LBB21_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a0, 25
; RV32IF-NEXT: .LBB21_2:
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_nonnegative_lui_addi:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: lui a1, 4
; RV32ZICOND-NEXT: addi a1, a1, -25
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: select_nonnegative_lui_addi:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: lui a2, 4
; RV32IXQCI-NEXT: li a1, 25
; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_nonnegative_lui_addi:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui a0, 4
; RV64I-NEXT: bgez a1, .LBB21_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: li a0, 25
; RV64I-NEXT: .LBB21_2:
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_nonnegative_lui_addi:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: mv a1, a0
; RV64IFD-NEXT: lui a0, 4
; RV64IFD-NEXT: bgez a1, .LBB21_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: li a0, 25
; RV64IFD-NEXT: .LBB21_2:
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: select_nonnegative_lui_addi:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: lui a1, 4
; RV64ZICOND-NEXT: addi a1, a1, -25
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
; RV64ZICOND-NEXT: addi a0, a0, 25
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 16384, i32 25
ret i32 %cond
}
define i32 @select_nonnegative_lui_addi_swapped(i32 signext %x) {
; RV32I-LABEL: select_nonnegative_lui_addi_swapped:
; RV32I: # %bb.0:
; RV32I-NEXT: bgez a0, .LBB22_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a0, 4
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB22_2:
; RV32I-NEXT: li a0, 25
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_nonnegative_lui_addi_swapped:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bgez a0, .LBB22_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, 4
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB22_2:
; RV32IF-NEXT: li a0, 25
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_nonnegative_lui_addi_swapped:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: lui a1, 4
; RV32ZICOND-NEXT: addi a1, a1, -25
; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: select_nonnegative_lui_addi_swapped:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a2, 25
; RV32IXQCI-NEXT: lui a1, 4
; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: select_nonnegative_lui_addi_swapped:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB22_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 4
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB22_2:
; RV64I-NEXT: li a0, 25
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_nonnegative_lui_addi_swapped:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bgez a0, .LBB22_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, 4
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB22_2:
; RV64IFD-NEXT: li a0, 25
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: select_nonnegative_lui_addi_swapped:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: lui a1, 4
; RV64ZICOND-NEXT: addi a1, a1, -25
; RV64ZICOND-NEXT: czero.eqz a0, a1, a0
; RV64ZICOND-NEXT: addi a0, a0, 25
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 25, i32 16384
ret i32 %cond
}
define i32 @diff_shl_addi(i32 signext %x) {
; RV32I-LABEL: diff_shl_addi:
; RV32I: # %bb.0:
; RV32I-NEXT: bgez a0, .LBB23_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a0, 4
; RV32I-NEXT: addi a0, a0, 25
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB23_2:
; RV32I-NEXT: li a0, 25
; RV32I-NEXT: ret
;
; RV32IF-LABEL: diff_shl_addi:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bgez a0, .LBB23_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, 4
; RV32IF-NEXT: addi a0, a0, 25
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB23_2:
; RV32IF-NEXT: li a0, 25
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: diff_shl_addi:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: slli a0, a0, 14
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: diff_shl_addi:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: lui a2, 4
; RV32IXQCI-NEXT: li a1, 25
; RV32IXQCI-NEXT: bgez a0, .LBB23_2
; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: addi a1, a2, 25
; RV32IXQCI-NEXT: .LBB23_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: diff_shl_addi:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB23_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 4
; RV64I-NEXT: addi a0, a0, 25
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB23_2:
; RV64I-NEXT: li a0, 25
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: diff_shl_addi:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bgez a0, .LBB23_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, 4
; RV64IFD-NEXT: addi a0, a0, 25
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB23_2:
; RV64IFD-NEXT: li a0, 25
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: diff_shl_addi:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: slli a0, a0, 14
; RV64ZICOND-NEXT: addiw a0, a0, 25
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 25, i32 16409
ret i32 %cond
}
define i32 @diff_shl_addi2(i32 signext %x) {
; RV32I-LABEL: diff_shl_addi2:
; RV32I: # %bb.0:
; RV32I-NEXT: bgez a0, .LBB24_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: li a0, 25
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB24_2:
; RV32I-NEXT: lui a0, 4
; RV32I-NEXT: addi a0, a0, 25
; RV32I-NEXT: ret
;
; RV32IF-LABEL: diff_shl_addi2:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bgez a0, .LBB24_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a0, 25
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB24_2:
; RV32IF-NEXT: lui a0, 4
; RV32IF-NEXT: addi a0, a0, 25
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: diff_shl_addi2:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: xori a0, a0, 1
; RV32ZICOND-NEXT: slli a0, a0, 14
; RV32ZICOND-NEXT: addi a0, a0, 25
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: diff_shl_addi2:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: lui a2, 4
; RV32IXQCI-NEXT: li a1, 25
; RV32IXQCI-NEXT: bltz a0, .LBB24_2
; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: addi a1, a2, 25
; RV32IXQCI-NEXT: .LBB24_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: diff_shl_addi2:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB24_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: li a0, 25
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB24_2:
; RV64I-NEXT: lui a0, 4
; RV64I-NEXT: addi a0, a0, 25
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: diff_shl_addi2:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bgez a0, .LBB24_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: li a0, 25
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB24_2:
; RV64IFD-NEXT: lui a0, 4
; RV64IFD-NEXT: addi a0, a0, 25
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: diff_shl_addi2:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: xori a0, a0, 1
; RV64ZICOND-NEXT: slli a0, a0, 14
; RV64ZICOND-NEXT: addiw a0, a0, 25
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 16409, i32 25
ret i32 %cond
}
define i32 @diff_pow2_24_16(i32 signext %x) {
; RV32-LABEL: diff_pow2_24_16:
; RV32: # %bb.0:
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: andi a0, a0, -8
; RV32-NEXT: addi a0, a0, 24
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: diff_pow2_24_16:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a2, 24
; RV32IXQCI-NEXT: li a1, 16
; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: diff_pow2_24_16:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: andi a0, a0, -8
; RV64-NEXT: addi a0, a0, 24
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 24, i32 16
ret i32 %cond
}
define i32 @diff_pow2_16_24(i32 signext %x) {
; RV32-LABEL: diff_pow2_16_24:
; RV32: # %bb.0:
; RV32-NEXT: srli a0, a0, 28
; RV32-NEXT: andi a0, a0, 8
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: diff_pow2_16_24:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a2, 16
; RV32IXQCI-NEXT: li a1, 24
; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: diff_pow2_16_24:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 60
; RV64-NEXT: andi a0, a0, 8
; RV64-NEXT: addiw a0, a0, 16
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 16, i32 24
ret i32 %cond
}
define i32 @zext_or_constant(i32 signext %x) {
; RV32I-LABEL: zext_or_constant:
; RV32I: # %bb.0:
; RV32I-NEXT: bgez a0, .LBB27_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a0, 140
; RV32I-NEXT: addi a0, a0, 417
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB27_2:
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: zext_or_constant:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bgez a0, .LBB27_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, 140
; RV32IF-NEXT: addi a0, a0, 417
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB27_2:
; RV32IF-NEXT: srli a0, a0, 31
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: zext_or_constant:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: lui a1, 140
; RV32ZICOND-NEXT: xori a2, a0, 1
; RV32ZICOND-NEXT: addi a1, a1, 417
; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: zext_or_constant:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: srli a2, a0, 31
; RV32IXQCI-NEXT: lui a1, 140
; RV32IXQCI-NEXT: addi a1, a1, 417
; RV32IXQCI-NEXT: bltz a0, .LBB27_2
; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: xori a1, a2, 1
; RV32IXQCI-NEXT: .LBB27_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: zext_or_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB27_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 140
; RV64I-NEXT: addi a0, a0, 417
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB27_2:
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: zext_or_constant:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bgez a0, .LBB27_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, 140
; RV64IFD-NEXT: addi a0, a0, 417
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB27_2:
; RV64IFD-NEXT: srli a0, a0, 63
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: zext_or_constant:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: lui a1, 140
; RV64ZICOND-NEXT: xori a2, a0, 1
; RV64ZICOND-NEXT: addi a1, a1, 417
; RV64ZICOND-NEXT: czero.eqz a0, a1, a0
; RV64ZICOND-NEXT: or a0, a2, a0
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%ext = zext i1 %cmp to i32
%cond = select i1 %cmp, i32 %ext, i32 573857
ret i32 %cond
}
define i32 @zext_or_constant2(i32 signext %x) {
; RV32I-LABEL: zext_or_constant2:
; RV32I: # %bb.0:
; RV32I-NEXT: bltz a0, .LBB28_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a0, 140
; RV32I-NEXT: addi a0, a0, 417
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB28_2:
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: zext_or_constant2:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bltz a0, .LBB28_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, 140
; RV32IF-NEXT: addi a0, a0, 417
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB28_2:
; RV32IF-NEXT: srli a0, a0, 31
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: zext_or_constant2:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: lui a1, 140
; RV32ZICOND-NEXT: xori a2, a0, 1
; RV32ZICOND-NEXT: addi a1, a1, 417
; RV32ZICOND-NEXT: czero.nez a1, a1, a0
; RV32ZICOND-NEXT: czero.eqz a0, a2, a0
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: zext_or_constant2:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: srli a2, a0, 31
; RV32IXQCI-NEXT: lui a1, 140
; RV32IXQCI-NEXT: addi a1, a1, 417
; RV32IXQCI-NEXT: bgez a0, .LBB28_2
; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: xori a1, a2, 1
; RV32IXQCI-NEXT: .LBB28_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: zext_or_constant2:
; RV64I: # %bb.0:
; RV64I-NEXT: bltz a0, .LBB28_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 140
; RV64I-NEXT: addi a0, a0, 417
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB28_2:
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: zext_or_constant2:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bltz a0, .LBB28_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, 140
; RV64IFD-NEXT: addi a0, a0, 417
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB28_2:
; RV64IFD-NEXT: srli a0, a0, 63
; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: zext_or_constant2:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: lui a1, 140
; RV64ZICOND-NEXT: xori a2, a0, 1
; RV64ZICOND-NEXT: addi a1, a1, 417
; RV64ZICOND-NEXT: czero.nez a1, a1, a0
; RV64ZICOND-NEXT: czero.eqz a0, a2, a0
; RV64ZICOND-NEXT: or a0, a1, a0
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%ext = zext i1 %cmp to i32
%cond = select i1 %cmp, i32 573857, i32 %ext
ret i32 %cond
}
define i32 @sext_or_constant(i32 signext %x) {
; RV32I-LABEL: sext_or_constant:
; RV32I: # %bb.0:
; RV32I-NEXT: bgez a0, .LBB29_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a0, 140
; RV32I-NEXT: addi a0, a0, 417
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB29_2:
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: sext_or_constant:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bgez a0, .LBB29_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, 140
; RV32IF-NEXT: addi a0, a0, 417
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB29_2:
; RV32IF-NEXT: srli a0, a0, 31
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: sext_or_constant:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: lui a1, 140
; RV32ZICOND-NEXT: addi a2, a0, -1
; RV32ZICOND-NEXT: addi a1, a1, 417
; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
; RV32ZICOND-NEXT: czero.nez a0, a2, a0
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: sext_or_constant:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: srli a2, a0, 31
; RV32IXQCI-NEXT: lui a1, 140
; RV32IXQCI-NEXT: addi a1, a1, 417
; RV32IXQCI-NEXT: bltz a0, .LBB29_2
; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: addi a1, a2, -1
; RV32IXQCI-NEXT: .LBB29_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: sext_or_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: bgez a0, .LBB29_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 140
; RV64I-NEXT: addi a0, a0, 417
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB29_2:
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: sext_or_constant:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bgez a0, .LBB29_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, 140
; RV64IFD-NEXT: addi a0, a0, 417
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB29_2:
; RV64IFD-NEXT: srli a0, a0, 63
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: sext_or_constant:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: lui a1, 140
; RV64ZICOND-NEXT: addi a2, a0, -1
; RV64ZICOND-NEXT: addi a1, a1, 417
; RV64ZICOND-NEXT: czero.eqz a1, a1, a0
; RV64ZICOND-NEXT: czero.nez a0, a2, a0
; RV64ZICOND-NEXT: or a0, a0, a1
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%ext = sext i1 %cmp to i32
%cond = select i1 %cmp, i32 %ext, i32 573857
ret i32 %cond
}
define i32 @sext_or_constant2(i32 signext %x) {
; RV32I-LABEL: sext_or_constant2:
; RV32I: # %bb.0:
; RV32I-NEXT: bltz a0, .LBB30_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a0, 140
; RV32I-NEXT: addi a0, a0, 417
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: sext_or_constant2:
; RV32IF: # %bb.0:
; RV32IF-NEXT: bltz a0, .LBB30_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, 140
; RV32IF-NEXT: addi a0, a0, 417
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB30_2:
; RV32IF-NEXT: srli a0, a0, 31
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: sext_or_constant2:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: lui a1, 140
; RV32ZICOND-NEXT: addi a2, a0, -1
; RV32ZICOND-NEXT: addi a1, a1, 417
; RV32ZICOND-NEXT: czero.nez a1, a1, a0
; RV32ZICOND-NEXT: czero.eqz a0, a2, a0
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: ret
;
; RV32IXQCI-LABEL: sext_or_constant2:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: srli a2, a0, 31
; RV32IXQCI-NEXT: lui a1, 140
; RV32IXQCI-NEXT: addi a1, a1, 417
; RV32IXQCI-NEXT: bgez a0, .LBB30_2
; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: addi a1, a2, -1
; RV32IXQCI-NEXT: .LBB30_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64I-LABEL: sext_or_constant2:
; RV64I: # %bb.0:
; RV64I-NEXT: bltz a0, .LBB30_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 140
; RV64I-NEXT: addi a0, a0, 417
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB30_2:
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: sext_or_constant2:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bltz a0, .LBB30_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, 140
; RV64IFD-NEXT: addi a0, a0, 417
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB30_2:
; RV64IFD-NEXT: srli a0, a0, 63
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: ret
;
; RV64ZICOND-LABEL: sext_or_constant2:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: lui a1, 140
; RV64ZICOND-NEXT: addi a2, a0, -1
; RV64ZICOND-NEXT: addi a1, a1, 417
; RV64ZICOND-NEXT: czero.nez a1, a1, a0
; RV64ZICOND-NEXT: czero.eqz a0, a2, a0
; RV64ZICOND-NEXT: or a0, a1, a0
; RV64ZICOND-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%ext = sext i1 %cmp to i32
%cond = select i1 %cmp, i32 573857, i32 %ext
ret i32 %cond
}
define i32 @select_0_6(i32 signext %x) {
; RV32-LABEL: select_0_6:
; RV32: # %bb.0:
; RV32-NEXT: srai a0, a0, 2
; RV32-NEXT: srli a0, a0, 30
; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_0_6:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, 6
; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 0
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_0_6:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 2
; RV64-NEXT: srli a0, a0, 62
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 0, i32 6
ret i32 %cond
}
define i32 @select_6_0(i32 signext %x) {
; RV32-LABEL: select_6_0:
; RV32: # %bb.0:
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: andi a0, a0, 6
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_6_0:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, 0
; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 6
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_6_0:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: andi a0, a0, 6
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 6, i32 0
ret i32 %cond
}
define i32 @select_0_394(i32 signext %x) {
; RV32-LABEL: select_0_394:
; RV32: # %bb.0:
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: andi a0, a0, 394
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_0_394:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, 394
; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 0
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_0_394:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: andi a0, a0, 394
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 0, i32 394
ret i32 %cond
}
define i32 @select_394_0(i32 signext %x) {
; RV32-LABEL: select_394_0:
; RV32: # %bb.0:
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: andi a0, a0, 394
; RV32-NEXT: ret
;
; RV32IXQCI-LABEL: select_394_0:
; RV32IXQCI: # %bb.0:
; RV32IXQCI-NEXT: li a1, 394
; RV32IXQCI-NEXT: qc.lilti a1, a0, 0, 0
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
;
; RV64-LABEL: select_394_0:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: andi a0, a0, 394
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 394, i32 0
ret i32 %cond
}
Reference in New Issue View Git Blame Copy Permalink