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llvm-project/llvm/test/CodeGen/RISCV/zibi.ll
Boyao Wang 27f8f9e1f1
[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858) 
This adds the CodeGen support of Zibi v0.1 experimental extension, which
depends on #127463.
2025-09-18 11:03:48 +08:00

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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=ZIBI,ZIBI-RV32 %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=ZIBI,ZIBI-RV64 %s
define void @test_bne_neg(ptr %b) nounwind {
; ZIBI-LABEL: test_bne_neg:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: bnei a1, -1, .LBB0_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB0_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp ne i32 %val1, -1
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_beq_neg(ptr %b) nounwind {
; ZIBI-LABEL: test_beq_neg:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: beqi a1, -1, .LBB1_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB1_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 %val1, -1
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_bne_zero(ptr %b) nounwind {
; ZIBI-LABEL: test_bne_zero:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: bnez a1, .LBB2_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB2_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp ne i32 %val1, 0
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_beq_zero(ptr %b) nounwind {
; ZIBI-LABEL: test_beq_zero:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: beqz a1, .LBB3_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB3_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 %val1, 0
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_bne_1(ptr %b) nounwind {
; ZIBI-LABEL: test_bne_1:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: bnei a1, 1, .LBB4_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB4_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp ne i32 %val1, 1
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_beq_1(ptr %b) nounwind {
; ZIBI-LABEL: test_beq_1:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: beqi a1, 1, .LBB5_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB5_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 %val1, 1
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_bne_31(ptr %b) nounwind {
; ZIBI-LABEL: test_bne_31:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: bnei a1, 31, .LBB6_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB6_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp ne i32 %val1, 31
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_beq_31(ptr %b) nounwind {
; ZIBI-LABEL: test_beq_31:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: beqi a1, 31, .LBB7_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB7_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 %val1, 31
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_bne_32(ptr %b) nounwind {
; ZIBI-LABEL: test_bne_32:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: li a2, 32
; ZIBI-NEXT: bne a1, a2, .LBB8_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB8_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp ne i32 %val1, 32
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
define void @test_beq_32(ptr %b) nounwind {
; ZIBI-LABEL: test_beq_32:
; ZIBI: # %bb.0:
; ZIBI-NEXT: lw a1, 0(a0)
; ZIBI-NEXT: li a2, 32
; ZIBI-NEXT: beq a1, a2, .LBB9_2
; ZIBI-NEXT: # %bb.1: # %test2
; ZIBI-NEXT: lw zero, 0(a0)
; ZIBI-NEXT: .LBB9_2: # %end
; ZIBI-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 %val1, 32
br i1 %tst1, label %end, label %test2, !prof !0
test2:
%val2 = load volatile i32, ptr %b
br label %end
end:
ret void
}
!0 = !{!"branch_weights", i32 1, i32 99}
define i32 @test_select_beq_neg(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_beq_neg:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: beqi a0, -1, .LBB10_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB10_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_beq_neg:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: beqi a3, -1, .LBB10_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB10_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp eq i32 %a, -1
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_bne_neg(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_bne_neg:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: bnei a0, -1, .LBB11_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB11_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_bne_neg:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: bnei a3, -1, .LBB11_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB11_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp ne i32 %a, -1
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_beq_zero(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_beq_zero:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: beqz a0, .LBB12_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB12_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_beq_zero:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: beqz a3, .LBB12_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB12_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp eq i32 %a, 0
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_bne_zero(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_bne_zero:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: bnez a0, .LBB13_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB13_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_bne_zero:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: bnez a3, .LBB13_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB13_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp ne i32 %a, 0
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_beq_1(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_beq_1:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: beqi a0, 1, .LBB14_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB14_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_beq_1:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: beqi a3, 1, .LBB14_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB14_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp eq i32 %a, 1
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_bne_1(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_bne_1:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: bnei a0, 1, .LBB15_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB15_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_bne_1:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: bnei a3, 1, .LBB15_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB15_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp ne i32 %a, 1
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_beq_31(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_beq_31:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: beqi a0, 31, .LBB16_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB16_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_beq_31:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: beqi a3, 31, .LBB16_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB16_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp eq i32 %a, 31
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_bne_31(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_bne_31:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: bnei a0, 31, .LBB17_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB17_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_bne_31:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: bnei a3, 31, .LBB17_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB17_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp ne i32 %a, 31
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_beq_32(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_beq_32:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: li a3, 32
; ZIBI-RV32-NEXT: beq a0, a3, .LBB18_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB18_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_beq_32:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: li a4, 32
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: beq a3, a4, .LBB18_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB18_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp eq i32 %a, 32
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
define i32 @test_select_bne_32(i32 %a, i32 %b, i32 %c) nounwind {
; ZIBI-RV32-LABEL: test_select_bne_32:
; ZIBI-RV32: # %bb.0:
; ZIBI-RV32-NEXT: li a3, 32
; ZIBI-RV32-NEXT: bne a0, a3, .LBB19_2
; ZIBI-RV32-NEXT: # %bb.1:
; ZIBI-RV32-NEXT: mv a1, a2
; ZIBI-RV32-NEXT: .LBB19_2:
; ZIBI-RV32-NEXT: mv a0, a1
; ZIBI-RV32-NEXT: ret
;
; ZIBI-RV64-LABEL: test_select_bne_32:
; ZIBI-RV64: # %bb.0:
; ZIBI-RV64-NEXT: sext.w a3, a0
; ZIBI-RV64-NEXT: li a4, 32
; ZIBI-RV64-NEXT: mv a0, a1
; ZIBI-RV64-NEXT: bne a3, a4, .LBB19_2
; ZIBI-RV64-NEXT: # %bb.1:
; ZIBI-RV64-NEXT: mv a0, a2
; ZIBI-RV64-NEXT: .LBB19_2:
; ZIBI-RV64-NEXT: ret
%tst = icmp ne i32 %a, 32
%ret = select i1 %tst, i32 %b, i32 %c
ret i32 %ret
}
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