977b546c32
Introduce a new SchedPredicate, `FeatureSchedPredicate`, that holds true
when a certain SubtargetFeature is enabled. This could be useful when we
want to configure a scheduling model with subtarget features.
I add this as a separate SchedPredicate rather than piggy-back on the
existing `SchedPredicate<[{....}]>` because first and foremost,
`SchedPredicate` is expected to only operate on MachineInstr, so it does
_not_ appear in `MCGenSubtargetInfo::resolveVariantSchedClass` but only
show up in `TargetGenSubtargetInfo::resolveSchedClass`. Yet I think
`FeatureSchedPredicate` will be useful for both MCInst and MachineInstr.
There is another subtle difference between `resolveVariantSchedClass`
and `resolveSchedClass` regarding how we access the MCSubtargetInfo
instance, if we really want to express `FeatureSchedPredicate` using
`SchedPredicate<[{.....}]>`.
So I thought it'll be easier to add another new SchedPredicate for
SubtargetFeature.
65 lines
2.2 KiB
TableGen
65 lines
2.2 KiB
TableGen
// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s -o - | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def FeatureFoo : SubtargetFeature<"foo", "HasFoo", "true", "enable foo">;
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def ResX0 : ProcResource<1>;
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let OutOperandList = (outs), InOperandList = (ins) in
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def Inst_A : Instruction;
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def SchedModel_A: SchedMachineModel {
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let CompleteModel = false;
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}
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let SchedModel = SchedModel_A in {
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def SchedWriteResA : SchedWriteRes<[ResX0]> {
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let Latency = 2;
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}
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def SchedWriteResB : SchedWriteRes<[ResX0]> {
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let Latency = 4;
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}
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// Check SchedPredicate with subtarget feature.
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def FeatureFooPred : FeatureSchedPredicate<FeatureFoo>;
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def Variant : SchedWriteVariant<[
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SchedVar<FeatureFooPred, [SchedWriteResA]>,
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SchedVar<NoSchedPred, [SchedWriteResB]>
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]>;
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def : InstRW<[Variant], (instrs Inst_A)>;
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}
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def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
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// CHECK: unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
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// CHECK-NEXT: const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID)
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// CHECK: case {{.*}}: // Inst_A
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// CHECK-NEXT: if (CPUID == {{.*}}) { // SchedModel_A
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// CHECK-NEXT: if (STI.hasFeature(TestTarget::FeatureFoo))
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// CHECK-NEXT: return {{.*}}; // SchedWriteResA
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// CHECK-NEXT: return {{.*}}; // SchedWriteResB
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// CHECK: unsigned resolveVariantSchedClass(unsigned SchedClass,
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// CHECK-NEXT: const MCInst *MI, const MCInstrInfo *MCII,
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// CHECK-NEXT: unsigned CPUID) const override {
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// CHECK-NEXT: return TestTarget_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
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// CHECK-NEXT: }
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// CHECK: unsigned TestTargetGenSubtargetInfo
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// CHECK-NEXT: ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
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// CHECK-NEXT: switch (SchedClass) {
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// CHECK-NEXT: case {{.*}}: // Inst_A
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// CHECK-NEXT: if (SchedModel->getProcessorID() == {{.*}}) { // SchedModel_A
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// CHECK-NEXT: if (this->hasFeature(TestTarget::FeatureFoo))
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// CHECK-NEXT: return {{.*}}; // SchedWriteResA
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// CHECK-NEXT: return {{.*}}; // SchedWriteResB
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