74af5784a5
This reverts commit f80c0baf058dbdc5 and 94eade61a02ae5. Recommit a small fix for targets using prefersVectorizedAddressing. Original message: Update VPReplicateRecipe::computeCost to compute costs of more replicating loads/stores. There are 2 cases that require extra checks to match the legacy cost model: 1. If the pointer is based on an induction, the legacy cost model passes its SCEV to getAddressComputationCost. In those cases, still fall back to the legacy cost. SCEV computations will be added as follow-up 2. If a load is used as part of an address of another load, the legacy cost model skips the scalarization overhead. Those cases are currently handled by a usedByLoadOrStore helper. Note that getScalarizationOverhead also needs updating, because when the legacy cost model computes the scalarization overhead, scalars have not been collected yet, so we can't each for replicating recipes to skip their cost, except other loads. This again can be further improved by modeling inserts/extracts explicitly and consistently, and compute costs for those operations directly where needed. PR: https://github.com/llvm/llvm-project/pull/160053
85 lines
3.3 KiB
LLVM
85 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -p loop-vectorize -S %s | FileCheck %s
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target triple = "armv7-unknown-linux-gnueabihf"
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define void @replicating_load_used_by_other_load(i32 %arg, ptr %a, i32 %b) {
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; CHECK-LABEL: define void @replicating_load_used_by_other_load(
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; CHECK-SAME: i32 [[ARG:%.*]], ptr [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[ARG]], %[[ENTRY]] ]
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[IV]], 1
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; CHECK-NEXT: [[AND_1:%.*]] = and i32 [[IV]], 1
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; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 [[IV]], 2
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; CHECK-NEXT: [[SHL_2:%.*]] = shl i32 [[IV]], 1
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; CHECK-NEXT: [[AND_2:%.*]] = and i32 [[SHL_2]], 2
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; CHECK-NEXT: [[OR_1:%.*]] = or i32 [[AND_2]], [[AND_1]]
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; CHECK-NEXT: [[OR_2:%.*]] = or i32 [[OR_1]], [[SHL_1]]
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; CHECK-NEXT: [[XOR_1:%.*]] = xor i32 [[B]], [[OR_2]]
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; CHECK-NEXT: [[XOR_2:%.*]] = xor i32 [[XOR_1]], [[ARG]]
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; CHECK-NEXT: [[SHR_2:%.*]] = lshr i32 [[SHL_1]], 1
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; CHECK-NEXT: [[XOR_3:%.*]] = xor i32 [[SHR]], [[ARG]]
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; CHECK-NEXT: [[AND_3:%.*]] = and i32 [[XOR_3]], 1
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; CHECK-NEXT: [[AND_4:%.*]] = and i32 [[IV]], 2147483646
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; CHECK-NEXT: [[OR_3:%.*]] = or i32 [[AND_3]], [[AND_4]]
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; CHECK-NEXT: [[AND_5:%.*]] = and i32 [[IV]], 254
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; CHECK-NEXT: [[SHL_3:%.*]] = shl i32 [[OR_3]], 1
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; CHECK-NEXT: [[XOR_4:%.*]] = xor i32 [[SHL_3]], 2
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; CHECK-NEXT: [[OR_4:%.*]] = or i32 [[AND_5]], [[XOR_4]]
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; CHECK-NEXT: [[XOR_5:%.*]] = xor i32 [[SHR_2]], [[OR_4]]
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; CHECK-NEXT: [[XOR_6:%.*]] = xor i32 [[XOR_5]], [[XOR_2]]
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; CHECK-NEXT: [[AND_6:%.*]] = and i32 [[XOR_6]], 255
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; CHECK-NEXT: [[XOR_7:%.*]] = xor i32 [[AND_6]], 1
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[A]], i32 [[XOR_7]]
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; CHECK-NEXT: [[LD:%.*]] = load i8, ptr [[GEP]], align 1
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[LD]] to i32
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; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i32, ptr null, i32 [[ZEXT]]
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; CHECK-NEXT: store i32 0, ptr [[GEP_2]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[IV_NEXT]], 100
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; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ %arg, %entry ]
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%shr = lshr i32 %iv, 1
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%and.1 = and i32 %iv, 1
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%shl.1 = shl i32 %iv, 2
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%shl.2 = shl i32 %iv, 1
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%and.2 = and i32 %shl.2, 2
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%or.1 = or i32 %and.2, %and.1
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%or.2 = or i32 %or.1, %shl.1
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%xor.1 = xor i32 %b, %or.2
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%xor.2 = xor i32 %xor.1, %arg
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%shr.2 = lshr i32 %shl.1, 1
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%xor.3 = xor i32 %shr, %arg
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%and.3 = and i32 %xor.3, 1
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%and.4 = and i32 %iv, 2147483646
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%or.3 = or i32 %and.3, %and.4
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%and.5 = and i32 %iv, 254
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%shl.3 = shl i32 %or.3, 1
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%xor.4 = xor i32 %shl.3, 2
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%or.4 = or i32 %and.5, %xor.4
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%xor.5 = xor i32 %shr.2, %or.4
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%xor.6 = xor i32 %xor.5, %xor.2
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%and.6 = and i32 %xor.6, 255
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%xor.7 = xor i32 %and.6, 1
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%gep = getelementptr i8, ptr %a, i32 %xor.7
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%ld = load i8, ptr %gep, align 1
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%zext = zext i8 %ld to i32
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%gep.2 = getelementptr i32, ptr null, i32 %zext
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store i32 0, ptr %gep.2, align 4
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%iv.next = add i32 %iv, 1
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%cmp = icmp eq i32 %iv.next, 100
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br i1 %cmp, label %exit, label %loop
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exit:
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ret void
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}
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