19c862dd27
We have accumulated four places where variables were only being used in asserts. This change silences the warnings for that.
609 lines
24 KiB
C++
609 lines
24 KiB
C++
//===--- CIRGenAsm.cpp - Inline Assembly Support for CIR CodeGen ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to emit inline assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "clang/Basic/DiagnosticSema.h"
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#include "CIRGenFunction.h"
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#include "clang/CIR/MissingFeatures.h"
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using namespace clang;
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using namespace clang::CIRGen;
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using namespace cir;
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static AsmFlavor inferFlavor(const CIRGenModule &cgm, const AsmStmt &s) {
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AsmFlavor gnuAsmFlavor =
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cgm.getCodeGenOpts().getInlineAsmDialect() == CodeGenOptions::IAD_ATT
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? AsmFlavor::x86_att
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: AsmFlavor::x86_intel;
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return isa<MSAsmStmt>(&s) ? AsmFlavor::x86_intel : gnuAsmFlavor;
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}
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static void collectClobbers(const CIRGenFunction &cgf, const AsmStmt &s,
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std::string &constraints, bool &hasUnwindClobber,
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bool &readOnly, bool readNone) {
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hasUnwindClobber = false;
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const CIRGenModule &cgm = cgf.getCIRGenModule();
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// Clobbers
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for (unsigned i = 0, e = s.getNumClobbers(); i != e; i++) {
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std::string clobber = s.getClobber(i);
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if (clobber == "memory") {
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readOnly = readNone = false;
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} else if (clobber == "unwind") {
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hasUnwindClobber = true;
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continue;
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} else if (clobber != "cc") {
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clobber = cgf.getTarget().getNormalizedGCCRegisterName(clobber);
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if (cgm.getCodeGenOpts().StackClashProtector &&
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cgf.getTarget().isSPRegName(clobber))
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cgm.getDiags().Report(s.getAsmLoc(),
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diag::warn_stack_clash_protection_inline_asm);
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}
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if (isa<MSAsmStmt>(&s)) {
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if (clobber == "eax" || clobber == "edx") {
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if (constraints.find("=&A") != std::string::npos)
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continue;
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std::string::size_type position1 =
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constraints.find("={" + clobber + "}");
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if (position1 != std::string::npos) {
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constraints.insert(position1 + 1, "&");
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continue;
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}
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std::string::size_type position2 = constraints.find("=A");
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if (position2 != std::string::npos) {
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constraints.insert(position2 + 1, "&");
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continue;
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}
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}
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}
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if (!constraints.empty())
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constraints += ',';
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constraints += "~{";
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constraints += clobber;
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constraints += '}';
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}
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// Add machine specific clobbers
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std::string_view machineClobbers = cgf.getTarget().getClobbers();
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if (!machineClobbers.empty()) {
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if (!constraints.empty())
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constraints += ',';
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constraints += machineClobbers;
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}
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}
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static void
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collectInOutConstraintInfos(const CIRGenFunction &cgf, const AsmStmt &s,
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SmallVectorImpl<TargetInfo::ConstraintInfo> &out,
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SmallVectorImpl<TargetInfo::ConstraintInfo> &in) {
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for (unsigned i = 0, e = s.getNumOutputs(); i != e; ++i) {
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StringRef name;
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if (const GCCAsmStmt *gas = dyn_cast<GCCAsmStmt>(&s))
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name = gas->getOutputName(i);
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TargetInfo::ConstraintInfo info(s.getOutputConstraint(i), name);
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// `validateOutputConstraint` modifies the `info` object by setting the
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// read/write, clobber, allows-register, and allows-memory process.
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bool isValid = cgf.getTarget().validateOutputConstraint(info);
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(void)isValid;
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assert(isValid && "Failed to parse output constraint");
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out.push_back(info);
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}
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for (unsigned i = 0, e = s.getNumInputs(); i != e; ++i) {
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StringRef name;
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if (const GCCAsmStmt *gas = dyn_cast<GCCAsmStmt>(&s))
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name = gas->getInputName(i);
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TargetInfo::ConstraintInfo info(s.getInputConstraint(i), name);
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// `validateInputConstraint` modifies the `info` object by setting the
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// read/write, clobber, allows-register, and allows-memory process.
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bool isValid = cgf.getTarget().validateInputConstraint(out, info);
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assert(isValid && "Failed to parse input constraint");
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(void)isValid;
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in.push_back(info);
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}
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}
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std::pair<mlir::Value, mlir::Type> CIRGenFunction::emitAsmInputLValue(
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const TargetInfo::ConstraintInfo &info, LValue inputValue,
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QualType inputType, std::string &constraintString, SourceLocation loc) {
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if (info.allowsRegister() || !info.allowsMemory()) {
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if (hasScalarEvaluationKind(inputType))
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return {emitLoadOfLValue(inputValue, loc).getValue(), mlir::Type()};
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mlir::Type ty = convertType(inputType);
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uint64_t size = cgm.getDataLayout().getTypeSizeInBits(ty);
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if ((size <= 64 && llvm::isPowerOf2_64(size)) ||
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getTargetHooks().isScalarizableAsmOperand(*this, ty)) {
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ty = cir::IntType::get(&getMLIRContext(), size, false);
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return {builder.createLoad(
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getLoc(loc),
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inputValue.getAddress().withElementType(builder, ty)),
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mlir::Type()};
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}
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}
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Address addr = inputValue.getAddress();
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constraintString += '*';
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return {addr.getPointer(), addr.getElementType()};
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}
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std::pair<mlir::Value, mlir::Type>
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CIRGenFunction::emitAsmInput(const TargetInfo::ConstraintInfo &info,
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const Expr *inputExpr,
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std::string &constraintString) {
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mlir::Location loc = getLoc(inputExpr->getExprLoc());
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// If this can't be a register or memory, i.e., has to be a constant
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// (immediate or symbolic), try to emit it as such.
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if (!info.allowsRegister() && !info.allowsMemory()) {
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if (info.requiresImmediateConstant()) {
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Expr::EvalResult evalResult;
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inputExpr->EvaluateAsRValue(evalResult, getContext(), true);
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llvm::APSInt intResult;
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if (evalResult.Val.toIntegralConstant(intResult, inputExpr->getType(),
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getContext()))
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return {builder.getConstInt(loc, intResult), mlir::Type()};
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}
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Expr::EvalResult result;
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if (inputExpr->EvaluateAsInt(result, getContext()))
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return {builder.getConstInt(loc, result.Val.getInt()), mlir::Type()};
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}
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if (info.allowsRegister() || !info.allowsMemory())
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if (CIRGenFunction::hasScalarEvaluationKind(inputExpr->getType()))
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return {emitScalarExpr(inputExpr), mlir::Type()};
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if (inputExpr->getStmtClass() == Expr::CXXThisExprClass)
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return {emitScalarExpr(inputExpr), mlir::Type()};
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inputExpr = inputExpr->IgnoreParenNoopCasts(getContext());
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LValue dest = emitLValue(inputExpr);
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return emitAsmInputLValue(info, dest, inputExpr->getType(), constraintString,
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inputExpr->getExprLoc());
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}
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static void emitAsmStores(CIRGenFunction &cgf, const AsmStmt &s,
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const llvm::ArrayRef<mlir::Value> regResults,
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const llvm::ArrayRef<mlir::Type> resultRegTypes,
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const llvm::ArrayRef<mlir::Type> resultTruncRegTypes,
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const llvm::ArrayRef<LValue> resultRegDests,
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const llvm::ArrayRef<QualType> resultRegQualTys,
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const llvm::BitVector &resultTypeRequiresCast,
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const llvm::BitVector &resultRegIsFlagReg) {
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CIRGenBuilderTy &builder = cgf.getBuilder();
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CIRGenModule &cgm = cgf.cgm;
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mlir::MLIRContext *ctx = builder.getContext();
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assert(regResults.size() == resultRegTypes.size());
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assert(regResults.size() == resultTruncRegTypes.size());
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assert(regResults.size() == resultRegDests.size());
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// ResultRegDests can be also populated by addReturnRegisterOutputs() above,
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// in which case its size may grow.
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assert(resultTypeRequiresCast.size() <= resultRegDests.size());
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assert(resultRegIsFlagReg.size() <= resultRegDests.size());
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for (unsigned i = 0, e = regResults.size(); i != e; ++i) {
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mlir::Value tmp = regResults[i];
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mlir::Type truncTy = resultTruncRegTypes[i];
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if (i < resultRegIsFlagReg.size() && resultRegIsFlagReg[i])
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assert(!cir::MissingFeatures::asmLLVMAssume());
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// If the result type of the LLVM IR asm doesn't match the result type of
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// the expression, do the conversion.
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if (resultRegTypes[i] != truncTy) {
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// Truncate the integer result to the right size, note that TruncTy can be
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// a pointer.
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if (mlir::isa<cir::FPTypeInterface>(truncTy)) {
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tmp = builder.createFloatingCast(tmp, truncTy);
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} else if (isa<cir::PointerType>(truncTy) &&
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isa<cir::IntType>(tmp.getType())) {
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uint64_t resSize = cgm.getDataLayout().getTypeSizeInBits(truncTy);
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tmp = builder.createIntCast(
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tmp, cir::IntType::get(ctx, (unsigned)resSize, false));
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tmp = builder.createIntToPtr(tmp, truncTy);
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} else if (isa<cir::PointerType>(tmp.getType()) &&
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isa<cir::IntType>(truncTy)) {
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uint64_t tmpSize = cgm.getDataLayout().getTypeSizeInBits(tmp.getType());
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tmp = builder.createPtrToInt(
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tmp, cir::IntType::get(ctx, (unsigned)tmpSize, false));
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tmp = builder.createIntCast(tmp, truncTy);
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} else if (isa<cir::IntType>(truncTy)) {
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tmp = builder.createIntCast(tmp, truncTy);
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} else if (isa<cir::VectorType>(truncTy)) {
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assert(!cir::MissingFeatures::asmVectorType());
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}
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}
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LValue dest = resultRegDests[i];
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// ResultTypeRequiresCast elements correspond to the first
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// ResultTypeRequiresCast.size() elements of RegResults.
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if ((i < resultTypeRequiresCast.size()) && resultTypeRequiresCast[i]) {
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unsigned size = cgf.getContext().getTypeSize(resultRegQualTys[i]);
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Address addr =
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dest.getAddress().withElementType(builder, resultRegTypes[i]);
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if (cgm.getTargetCIRGenInfo().isScalarizableAsmOperand(cgf, truncTy)) {
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builder.createStore(cgf.getLoc(s.getAsmLoc()), tmp, addr);
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continue;
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}
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QualType ty =
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cgf.getContext().getIntTypeForBitwidth(size, /*Signed=*/false);
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if (ty.isNull()) {
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const Expr *outExpr = s.getOutputExpr(i);
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cgm.getDiags().Report(outExpr->getExprLoc(),
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diag::err_store_value_to_reg);
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return;
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}
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dest = cgf.makeAddrLValue(addr, ty);
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}
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cgf.emitStoreThroughLValue(RValue::get(tmp), dest);
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}
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}
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mlir::LogicalResult CIRGenFunction::emitAsmStmt(const AsmStmt &s) {
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// Assemble the final asm string.
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std::string asmString = s.generateAsmString(getContext());
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SourceLocation srcLoc = s.getAsmLoc();
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mlir::Location loc = getLoc(srcLoc);
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// Get all the output and input constraints together.
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SmallVector<TargetInfo::ConstraintInfo> outputConstraintInfos;
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SmallVector<TargetInfo::ConstraintInfo> inputConstraintInfos;
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collectInOutConstraintInfos(*this, s, outputConstraintInfos,
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inputConstraintInfos);
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bool isGCCAsmGoto = false;
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std::string constraints;
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SmallVector<LValue> resultRegDests;
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SmallVector<QualType> resultRegQualTys;
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SmallVector<mlir::Type> resultRegTypes;
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SmallVector<mlir::Type> resultTruncRegTypes;
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SmallVector<mlir::Type> argTypes;
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SmallVector<mlir::Type> argElemTypes;
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SmallVector<mlir::Value> args;
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SmallVector<mlir::Value> outArgs;
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SmallVector<mlir::Value> inArgs;
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SmallVector<mlir::Value> inOutArgs;
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llvm::BitVector resultTypeRequiresCast;
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llvm::BitVector resultRegIsFlagReg;
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// Keep track of input constraints.
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std::string inOutConstraints;
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SmallVector<mlir::Type> inOutArgTypes;
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SmallVector<mlir::Type> inOutArgElemTypes;
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// Keep track of out constraints for tied input operand.
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SmallVector<std::string> outputConstraints;
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// Keep track of defined physregs.
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llvm::SmallSet<std::string, 8> physRegOutputs;
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// An inline asm can be marked readonly if it meets the following conditions:
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// - it doesn't have any sideeffects
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// - it doesn't clobber memory
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// - it doesn't return a value by-reference
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// It can be marked readnone if it doesn't have any input memory constraints
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// in addition to meeting the conditions listed above.
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bool readOnly = true, readNone = true;
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std::string outputConstraint;
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for (unsigned i = 0, e = s.getNumOutputs(); i != e; ++i) {
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TargetInfo::ConstraintInfo &info = outputConstraintInfos[i];
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// Simplify the output constraint.
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outputConstraint = s.getOutputConstraint(i);
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outputConstraint = getTarget().simplifyConstraint(
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StringRef(outputConstraint).drop_front());
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const Expr *outExpr = s.getOutputExpr(i);
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outExpr = outExpr->IgnoreParenNoopCasts(getContext());
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std::string gccReg;
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outputConstraint = s.addVariableConstraints(
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outputConstraint, *outExpr, getTarget(), info.earlyClobber(),
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[&](const Stmt *unspStmt, StringRef msg) {
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cgm.errorUnsupported(unspStmt, msg);
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},
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&gccReg);
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// Give an error on multiple outputs to same physreg.
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if (!gccReg.empty() && !physRegOutputs.insert(gccReg).second)
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cgm.error(srcLoc, "multiple outputs to hard register: " + gccReg);
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outputConstraints.push_back(outputConstraint);
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LValue dest = emitLValue(outExpr);
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if (!constraints.empty())
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constraints += ',';
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// If this is a register output, then make the inline a sm return it
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// by-value. If this is a memory result, return the value by-reference.
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QualType qty = outExpr->getType();
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const bool isScalarOrAggregate =
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hasScalarEvaluationKind(qty) || hasAggregateEvaluationKind(qty);
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if (!info.allowsMemory() && isScalarOrAggregate) {
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constraints += "=" + outputConstraint;
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resultRegQualTys.push_back(qty);
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resultRegDests.push_back(dest);
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bool isFlagReg = llvm::StringRef(outputConstraint).starts_with("{@cc");
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resultRegIsFlagReg.push_back(isFlagReg);
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mlir::Type ty = convertTypeForMem(qty);
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const bool requiresCast =
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info.allowsRegister() &&
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(cgm.getTargetCIRGenInfo().isScalarizableAsmOperand(*this, ty) ||
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isa<cir::RecordType, cir::ArrayType>(ty));
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resultTruncRegTypes.push_back(ty);
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resultTypeRequiresCast.push_back(requiresCast);
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if (requiresCast) {
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unsigned size = getContext().getTypeSize(qty);
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if (size == 0)
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cgm.error(outExpr->getExprLoc(), "output size should not be zero");
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ty = cir::IntType::get(&getMLIRContext(), size, false);
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}
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resultRegTypes.push_back(ty);
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// If this output is tied to an input, and if the input is larger, then
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// we need to set the actual result type of the inline asm node to be the
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// same as the input type.
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if (info.hasMatchingInput()) {
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unsigned inputNo;
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for (inputNo = 0; inputNo != s.getNumInputs(); ++inputNo) {
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TargetInfo::ConstraintInfo &input = inputConstraintInfos[inputNo];
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if (input.hasTiedOperand() && input.getTiedOperand() == i)
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break;
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}
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assert(inputNo != s.getNumInputs() && "Didn't find matching input!");
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QualType inputTy = s.getInputExpr(inputNo)->getType();
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QualType outputType = outExpr->getType();
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uint64_t inputSize = getContext().getTypeSize(inputTy);
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if (getContext().getTypeSize(outputType) < inputSize) {
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// Form the asm to return the value as a larger integer or fp type.
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resultRegTypes.back() = convertType(inputTy);
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}
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if (mlir::Type adjTy = cgm.getTargetCIRGenInfo().adjustInlineAsmType(
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*this, outputConstraint, resultRegTypes.back()))
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resultRegTypes.back() = adjTy;
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else
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cgm.getDiags().Report(srcLoc, diag::err_asm_invalid_type_in_input)
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<< outExpr->getType() << outputConstraint;
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}
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// Update largest vector width for any vector types.
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assert(!cir::MissingFeatures::asmVectorType());
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} else {
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Address destAddr = dest.getAddress();
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// Matrix types in memory are represented by arrays, but accessed through
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// vector pointers, with the alignment specified on the access operation.
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// For inline assembly, update pointer arguments to use vector pointers.
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// Otherwise there will be a mis-match if the matrix is also an
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// input-argument which is represented as vector.
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if (isa<MatrixType>(outExpr->getType().getCanonicalType()))
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destAddr =
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destAddr.withElementType(builder, convertType(outExpr->getType()));
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argTypes.push_back(destAddr.getType());
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argElemTypes.push_back(destAddr.getElementType());
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outArgs.push_back(destAddr.getPointer());
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args.push_back(destAddr.getPointer());
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constraints += "=*";
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constraints += outputConstraint;
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readOnly = readNone = false;
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}
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if (info.isReadWrite()) {
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inOutConstraints += ',';
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const Expr *inputExpr = s.getOutputExpr(i);
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// argValue: mlir::Value, argElementType: mlir::Type.
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auto [argValue, argElementType] =
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emitAsmInputLValue(info, dest, inputExpr->getType(), inOutConstraints,
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inputExpr->getExprLoc());
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if (mlir::Type adjTy = getTargetHooks().adjustInlineAsmType(
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*this, outputConstraint, argValue.getType()))
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argValue = builder.createBitcast(argValue, adjTy);
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// Update largest vector width for any vector types.
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assert(!cir::MissingFeatures::asmVectorType());
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// Only tie earlyclobber physregs.
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if (info.allowsRegister() && (gccReg.empty() || info.earlyClobber()))
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inOutConstraints += llvm::utostr(i);
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else
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inOutConstraints += outputConstraint;
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inOutArgTypes.push_back(argValue.getType());
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inOutArgElemTypes.push_back(argElementType);
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inOutArgs.push_back(argValue);
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}
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} // iterate over output operands
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for (unsigned i = 0, e = s.getNumInputs(); i != e; ++i) {
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TargetInfo::ConstraintInfo &info = inputConstraintInfos[i];
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const Expr *inputExpr = s.getInputExpr(i);
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|
|
if (info.allowsMemory())
|
|
readNone = false;
|
|
|
|
if (!constraints.empty())
|
|
constraints += ',';
|
|
|
|
std::string inputConstraint(s.getInputConstraint(i));
|
|
inputConstraint =
|
|
getTarget().simplifyConstraint(inputConstraint, &outputConstraintInfos);
|
|
|
|
inputConstraint = s.addVariableConstraints(
|
|
inputConstraint, *inputExpr->IgnoreParenNoopCasts(getContext()),
|
|
getTarget(), /*EarlyClobber=*/false,
|
|
[&](const Stmt *unspStmt, StringRef msg) {
|
|
cgm.errorUnsupported(unspStmt, msg);
|
|
});
|
|
|
|
std::string replaceConstraint(inputConstraint);
|
|
// argValue: mlir::Value, argElementType: mlir::Type.
|
|
auto [argValue, argElemType] = emitAsmInput(info, inputExpr, constraints);
|
|
|
|
// If this input argument is tied to a larger output result, extend the
|
|
// input to be the same size as the output. The LLVM backend wants to see
|
|
// the input and output of a matching constraint be the same size. Note
|
|
// that GCC does not define what the top bits are here. We use zext because
|
|
// that is usually cheaper, but LLVM IR should really get an anyext someday.
|
|
if (info.hasTiedOperand()) {
|
|
unsigned output = info.getTiedOperand();
|
|
QualType outputType = s.getOutputExpr(output)->getType();
|
|
QualType inputTy = inputExpr->getType();
|
|
|
|
if (getContext().getTypeSize(outputType) >
|
|
getContext().getTypeSize(inputTy)) {
|
|
// Use ptrtoint as appropriate so that we can do our extension.
|
|
if (isa<cir::PointerType>(argValue.getType()))
|
|
argValue = builder.createPtrToInt(argValue, uIntPtrTy);
|
|
mlir::Type outputTy = convertType(outputType);
|
|
if (isa<cir::IntType>(outputTy))
|
|
argValue = builder.createIntCast(argValue, outputTy);
|
|
else if (isa<cir::PointerType>(outputTy))
|
|
argValue = builder.createIntCast(argValue, uIntPtrTy);
|
|
else if (isa<cir::FPTypeInterface>(outputTy))
|
|
argValue = builder.createFloatingCast(argValue, outputTy);
|
|
}
|
|
|
|
// Deal with the tied operands' constraint code in adjustInlineAsmType.
|
|
replaceConstraint = outputConstraints[output];
|
|
}
|
|
|
|
if (mlir::Type adjTy = getTargetHooks().adjustInlineAsmType(
|
|
*this, replaceConstraint, argValue.getType()))
|
|
argValue = builder.createBitcast(argValue, adjTy);
|
|
else
|
|
cgm.getDiags().Report(s.getAsmLoc(), diag::err_asm_invalid_type_in_input)
|
|
<< inputExpr->getType() << inputConstraint;
|
|
|
|
// Update largest vector width for any vector types.
|
|
assert(!cir::MissingFeatures::asmVectorType());
|
|
|
|
argTypes.push_back(argValue.getType());
|
|
argElemTypes.push_back(argElemType);
|
|
inArgs.push_back(argValue);
|
|
args.push_back(argValue);
|
|
constraints += inputConstraint;
|
|
} // iterate over input operands
|
|
|
|
// Append the "input" part of inout constraints.
|
|
for (unsigned i = 0, e = inOutArgs.size(); i != e; ++i) {
|
|
args.push_back(inOutArgs[i]);
|
|
argTypes.push_back(inOutArgTypes[i]);
|
|
argElemTypes.push_back(inOutArgElemTypes[i]);
|
|
}
|
|
constraints += inOutConstraints;
|
|
|
|
bool hasUnwindClobber = false;
|
|
collectClobbers(*this, s, constraints, hasUnwindClobber, readOnly, readNone);
|
|
|
|
std::array<mlir::ValueRange, 3> operands = {outArgs, inArgs, inOutArgs};
|
|
|
|
mlir::Type resultType;
|
|
|
|
if (resultRegTypes.size() == 1)
|
|
resultType = resultRegTypes[0];
|
|
else if (resultRegTypes.size() > 1)
|
|
resultType = builder.getAnonRecordTy(resultRegTypes, /*packed=*/false,
|
|
/*padded=*/false);
|
|
|
|
bool hasSideEffect = s.isVolatile() || s.getNumOutputs() == 0;
|
|
|
|
std::vector<mlir::Value> regResults;
|
|
cir::InlineAsmOp ia = cir::InlineAsmOp::create(
|
|
builder, getLoc(s.getAsmLoc()), resultType, operands, asmString,
|
|
constraints, hasSideEffect, inferFlavor(cgm, s), mlir::ArrayAttr());
|
|
|
|
if (isGCCAsmGoto) {
|
|
assert(!cir::MissingFeatures::asmGoto());
|
|
} else if (hasUnwindClobber) {
|
|
assert(!cir::MissingFeatures::asmUnwindClobber());
|
|
} else {
|
|
assert(!cir::MissingFeatures::asmMemoryEffects());
|
|
|
|
mlir::Value result;
|
|
if (ia.getNumResults())
|
|
result = ia.getResult(0);
|
|
|
|
llvm::SmallVector<mlir::Attribute> operandAttrs;
|
|
|
|
int i = 0;
|
|
for (auto typ : argElemTypes) {
|
|
if (typ) {
|
|
[[maybe_unused]] mlir::Value op = args[i++];
|
|
assert(mlir::isa<cir::PointerType>(op.getType()) &&
|
|
"pointer type expected");
|
|
assert(cast<cir::PointerType>(op.getType()).getPointee() == typ &&
|
|
"element type differs from pointee type!");
|
|
|
|
operandAttrs.push_back(mlir::UnitAttr::get(&getMLIRContext()));
|
|
} else {
|
|
// We need to add an attribute for every arg since later, during
|
|
// the lowering to LLVM IR the attributes will be assigned to the
|
|
// CallInsn argument by index, i.e. we can't skip null type here
|
|
operandAttrs.push_back(mlir::Attribute());
|
|
}
|
|
}
|
|
assert(args.size() == operandAttrs.size() &&
|
|
"The number of attributes is not even with the number of operands");
|
|
|
|
ia.setOperandAttrsAttr(builder.getArrayAttr(operandAttrs));
|
|
|
|
if (resultRegTypes.size() == 1) {
|
|
regResults.push_back(result);
|
|
} else if (resultRegTypes.size() > 1) {
|
|
CharUnits alignment = CharUnits::One();
|
|
mlir::Value dest =
|
|
emitAlloca("__asm_result", resultType, loc, alignment, false);
|
|
Address addr = Address(dest, alignment);
|
|
builder.createStore(loc, result, addr);
|
|
|
|
for (unsigned i = 0, e = resultRegTypes.size(); i != e; ++i) {
|
|
cir::PointerType typ = builder.getPointerTo(resultRegTypes[i]);
|
|
cir::GetMemberOp ptr = builder.createGetMember(loc, typ, dest, "", i);
|
|
cir::LoadOp tmp = builder.createLoad(loc, Address(ptr, alignment));
|
|
regResults.push_back(tmp);
|
|
}
|
|
}
|
|
}
|
|
|
|
emitAsmStores(*this, s, regResults, resultRegTypes, resultTruncRegTypes,
|
|
resultRegDests, resultRegQualTys, resultTypeRequiresCast,
|
|
resultRegIsFlagReg);
|
|
|
|
return mlir::success();
|
|
}
|