98d3a25f74
This follows similar reasoning as 45ce88758d24 (https://github.com/llvm/llvm-project/pull/159556): LV does not preserve LCSSA, it constructs it just before processing a loop to vectorize. Runtime check expressions are invariant to that loop, so expanding them should not break LCSSA form for the loop we are about to vectorize. LV creates SCEV and memory runtime checks early on and then disconnects the blocks temporarily. The patch fixes a mis-compile, where previously LCSSA construction during SCEV expand may replace uses in currently unreachable SCEV/memory check blocks. Fixes https://github.com/llvm/llvm-project/issues/162512 PR: https://github.com/llvm/llvm-project/pull/165505
111 lines
5.5 KiB
LLVM
111 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes='print<scalar-evolution>,loop-vectorize' -force-vector-width=4 -scalar-evolution-classify-expressions=false -S %s | FileCheck %s
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; Test case for https://github.com/llvm/llvm-project/issues/119665.
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; %loop.2's backedge-taken-count depends on %add.1 from %loop.1 via its
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; corresponding SCEV at the scope of %loop.2. After vectorizing %loop.1, %add.1
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; isn't available at the entry of %loop.2 anymore and %add.1 at %loop.2's scope
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; must be invalidated, as well as %loop.2's backedge-taken count.
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define void @test_invalidate_scevs_at_scope(ptr %p) {
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; CHECK-LABEL: define void @test_invalidate_scevs_at_scope(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP_1:.*]]
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; CHECK: [[LOOP_1]]:
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; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 100, %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[TMP4]], [[IV_1]]
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; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1
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; CHECK-NEXT: [[C_1:%.*]] = icmp eq i32 [[IV_1]], 100
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; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT_1:.*]], label %[[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT_1]]:
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; CHECK-NEXT: [[ADD_LCSSA1:%.*]] = phi i32 [ [[ADD_1]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[ADD_LCSSA:%.*]] = add i32 [[TMP4]], 100
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; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD_LCSSA]], i32 100)
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[SMAX]], -100
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; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[TMP3]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
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; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[TMP6]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP7]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH2:.*]]
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; CHECK: [[VECTOR_PH2]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP7]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP7]], [[N_MOD_VF]]
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; CHECK-NEXT: br label %[[VECTOR_BODY3:.*]]
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; CHECK: [[VECTOR_BODY3]]:
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; CHECK-NEXT: [[INDEX5:%.*]] = phi i64 [ 0, %[[VECTOR_PH2]] ], [ [[INDEX_NEXT8:%.*]], %[[VECTOR_BODY3]] ]
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; CHECK-NEXT: [[VEC_IND6:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH2]] ], [ [[VEC_IND_NEXT7:%.*]], %[[VECTOR_BODY3]] ]
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[P]], i64 [[INDEX5]]
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; CHECK-NEXT: store <4 x i64> [[VEC_IND6]], ptr [[TMP9]], align 4
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; CHECK-NEXT: [[INDEX_NEXT8]] = add nuw i64 [[INDEX5]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT7]] = add <4 x i64> [[VEC_IND6]], splat (i64 4)
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT8]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK6:.*]], label %[[VECTOR_BODY3]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK6]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP7]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT_2:.*]], label %[[SCALAR_PH1]]
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; CHECK: [[SCALAR_PH1]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK6]] ], [ 0, %[[EXIT_1]] ]
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; CHECK-NEXT: br label %[[LOOP_2:.*]]
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; CHECK: [[LOOP_2]]:
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; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]
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; CHECK-NEXT: [[IV_2_TRUNC:%.*]] = trunc i64 [[IV_2]] to i32
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; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 1
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[P]], i64 [[IV_2]]
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; CHECK-NEXT: store i64 [[IV_2]], ptr [[GEP]], align 4
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; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD_LCSSA1]], [[IV_2_TRUNC]]
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; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[ADD_2]], 100
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; CHECK-NEXT: br i1 [[C_2]], label %[[LOOP_2]], label %[[EXIT_2]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: [[EXIT_2]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.1
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loop.1:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1 ]
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%1 = load i32, ptr %p, align 4
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%add.1 = add i32 %1, %iv.1
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%iv.1.next = add i32 %iv.1, 1
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%c.1 = icmp eq i32 %iv.1, 100
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br i1 %c.1, label %exit.1, label %loop.1
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exit.1:
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%add.lcssa = phi i32 [ %add.1, %loop.1 ]
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br label %loop.2
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loop.2:
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%iv.2 = phi i64 [ 0, %exit.1 ], [ %iv.2.next, %loop.2 ]
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%iv.2.trunc = trunc i64 %iv.2 to i32
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%iv.2.next = add i64 %iv.2, 1
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%gep = getelementptr inbounds i64, ptr %p, i64 %iv.2
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store i64 %iv.2, ptr %gep
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%add.2 = add i32 %add.lcssa, %iv.2.trunc
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%c.2 = icmp slt i32 %add.2, 100
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br i1 %c.2, label %loop.2, label %exit.2
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exit.2:
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ret void
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
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; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
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;.
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