22c091fc3c
Logic to load 32-bit and 64-bit immediates is currently present in RISCVAsmParser::emitLoadImm in order to support the li pseudoinstruction. With the introduction of RV64 codegen, there is a greater benefit of sharing immediate materialisation logic between the MC layer and codegen. The generateInstSeq helper allows this by producing a vector of simple structs representing the chosen instructions. This can then be consumed in the MC layer to produce MCInsts or at instruction selection time to produce appropriate SelectionDAG node. Sharing this logic means that both the li pseudoinstruction and codegen can benefit from future optimisations, and that this logic can be used for materialising constants during RV64 codegen. This patch does contain a behaviour change: addi will now be produced on RV64 when no lui is necessary to materialise the constant. In that case addiw takes x0 as the source register, so is semantically identical to addi. Differential Revision: https://reviews.llvm.org/D52961 llvm-svn: 346937
37 lines
1.1 KiB
C++
37 lines
1.1 KiB
C++
//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MATINT_H
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#define LLVM_LIB_TARGET_RISCV_MATINT_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cstdint>
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namespace llvm {
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namespace RISCVMatInt {
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struct Inst {
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unsigned Opc;
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int64_t Imm;
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Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
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};
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using InstSeq = SmallVector<Inst, 8>;
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// Helper to generate an instruction sequence that will materialise the given
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// immediate value into a register. A sequence of instructions represented by
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// a simple struct produced rather than directly emitting the instructions in
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// order to allow this helper to be used from both the MC layer and during
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// instruction selection.
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void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
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} // namespace RISCVMatInt
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} // namespace llvm
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#endif
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