56d0ed2a50
Summary: This is patch #3 of the new DivergenceAnalysis <https://lists.llvm.org/pipermail/llvm-dev/2018-May/123606.html> The GPUDivergenceAnalysis is intended to eventually supersede the existing LegacyDivergenceAnalysis. The existing LegacyDivergenceAnalysis produces incorrect results on unstructured Control-Flow Graphs: <https://bugs.llvm.org/show_bug.cgi?id=37185> This patch adds the option -use-gpu-divergence-analysis to the LegacyDivergenceAnalysis to turn it into a transparent wrapper for the GPUDivergenceAnalysis. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: jholewinski, jvesely, jfb, llvm-commits, alex-t, sameerds, arsenm, nhaehnle Differential Revision: https://reviews.llvm.org/D53493 llvm-svn: 348048
104 lines
4.3 KiB
LLVM
104 lines
4.3 KiB
LLVM
;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.swap(
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define float @buffer_atomic_swap(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.add(
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define float @buffer_atomic_add(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.sub(
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define float @buffer_atomic_sub(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.smin(
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define float @buffer_atomic_smin(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.umin(
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define float @buffer_atomic_umin(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.umin(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.smax(
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define float @buffer_atomic_smax(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.smax(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.umax(
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define float @buffer_atomic_umax(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.umax(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.and(
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define float @buffer_atomic_and(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.and(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.or(
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define float @buffer_atomic_or(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.or(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.xor(
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define float @buffer_atomic_xor(<4 x i32> inreg %rsrc, i32 inreg %data) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.xor(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(
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define float @buffer_atomic_cmpswap(<4 x i32> inreg %rsrc, i32 inreg %data, i32 inreg %cmp) #0 {
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main_body:
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%orig = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%r = bitcast i32 %orig to float
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ret float %r
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}
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declare i32 @llvm.amdgcn.buffer.atomic.swap(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.add(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.smin(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.umin(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.smax(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.umax(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.and(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.or(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.xor(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32, i32, <4 x i32>, i32, i32, i1) #0
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attributes #0 = { nounwind }
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