97ed076dd1
Field ResourceUnitMask was incorrectly defined as a 'const unsigned' mask. It should have been a 64 bit quantity instead. That means, ResourceUnitMask was always implicitly truncated to a 32 bit quantity. This issue has been found by inspection. Surprisingly, that bug was latent, and it never negatively affected any existing upstream targets. This patch fixes the wrong definition of ResourceUnitMask, and adds a bunch of extra debug prints to help debugging potential issues related to invalid processor resource masks. llvm-svn: 350820
92 lines
3.6 KiB
C++
92 lines
3.6 KiB
C++
//===--------------------- SummaryView.cpp -------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements the functionalities used by the SummaryView to print
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/// the report information.
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///
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//===----------------------------------------------------------------------===//
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#include "Views/SummaryView.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MCA/Support.h"
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#include "llvm/Support/Format.h"
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namespace llvm {
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namespace mca {
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#define DEBUG_TYPE "llvm-mca"
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SummaryView::SummaryView(const MCSchedModel &Model, ArrayRef<MCInst> S,
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unsigned Width)
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: SM(Model), Source(S), DispatchWidth(Width), LastInstructionIdx(0),
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TotalCycles(0), NumMicroOps(0),
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ProcResourceUsage(Model.getNumProcResourceKinds(), 0),
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ProcResourceMasks(Model.getNumProcResourceKinds()) {
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computeProcResourceMasks(SM, ProcResourceMasks);
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}
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void SummaryView::onEvent(const HWInstructionEvent &Event) {
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if (Event.Type == HWInstructionEvent::Dispatched)
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LastInstructionIdx = Event.IR.getSourceIndex();
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// We are only interested in the "instruction retired" events generated by
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// the retire stage for instructions that are part of iteration #0.
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if (Event.Type != HWInstructionEvent::Retired ||
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Event.IR.getSourceIndex() >= Source.size())
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return;
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// Update the cumulative number of resource cycles based on the processor
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// resource usage information available from the instruction descriptor. We
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// need to compute the cumulative number of resource cycles for every
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// processor resource which is consumed by an instruction of the block.
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const Instruction &Inst = *Event.IR.getInstruction();
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const InstrDesc &Desc = Inst.getDesc();
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NumMicroOps += Desc.NumMicroOps;
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for (const std::pair<uint64_t, const ResourceUsage> &RU : Desc.Resources) {
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if (RU.second.size()) {
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const auto It = find(ProcResourceMasks, RU.first);
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assert(It != ProcResourceMasks.end() &&
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"Invalid processor resource mask!");
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ProcResourceUsage[std::distance(ProcResourceMasks.begin(), It)] +=
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RU.second.size();
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}
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}
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}
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void SummaryView::printView(raw_ostream &OS) const {
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unsigned Instructions = Source.size();
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unsigned Iterations = (LastInstructionIdx / Instructions) + 1;
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unsigned TotalInstructions = Instructions * Iterations;
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unsigned TotalUOps = NumMicroOps * Iterations;
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double IPC = (double)TotalInstructions / TotalCycles;
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double UOpsPerCycle = (double)TotalUOps / TotalCycles;
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double BlockRThroughput = computeBlockRThroughput(
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SM, DispatchWidth, NumMicroOps, ProcResourceUsage);
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std::string Buffer;
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raw_string_ostream TempStream(Buffer);
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TempStream << "Iterations: " << Iterations;
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TempStream << "\nInstructions: " << TotalInstructions;
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TempStream << "\nTotal Cycles: " << TotalCycles;
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TempStream << "\nTotal uOps: " << TotalUOps << '\n';
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TempStream << "\nDispatch Width: " << DispatchWidth;
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TempStream << "\nuOps Per Cycle: "
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<< format("%.2f", floor((UOpsPerCycle * 100) + 0.5) / 100);
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TempStream << "\nIPC: "
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<< format("%.2f", floor((IPC * 100) + 0.5) / 100);
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TempStream << "\nBlock RThroughput: "
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<< format("%.1f", floor((BlockRThroughput * 10) + 0.5) / 10)
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<< '\n';
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TempStream.flush();
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OS << Buffer;
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}
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} // namespace mca.
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} // namespace llvm
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