fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
75 lines
2.6 KiB
LLVM
75 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX10 %s
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define void @temporal_divergent_i32(float %val, ptr %addr) {
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; GFX10-LABEL: temporal_divergent_i32:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_mov_b32 s5, -1
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; GFX10-NEXT: s_mov_b32 s4, 0
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; GFX10-NEXT: .LBB0_1: ; %loop
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; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-NEXT: s_add_i32 s5, s5, 1
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; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s5
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; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v0
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; GFX10-NEXT: v_mov_b32_e32 v3, s5
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; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4
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; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: s_cbranch_execnz .LBB0_1
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; GFX10-NEXT: ; %bb.2: ; %exit
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: flat_store_dword v[1:2], v3
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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br label %loop
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loop:
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%counter = phi i32 [ 0, %entry ], [ %counter.plus.1, %loop ]
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%f.counter = uitofp i32 %counter to float
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%cond = fcmp ogt float %f.counter, %val
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%counter.plus.1 = add i32 %counter, 1
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br i1 %cond, label %exit, label %loop
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exit:
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store i32 %counter, ptr %addr
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ret void
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}
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define void @temporal_divergent_i32_multiple_use(float %val, ptr %addr, ptr %addr2) {
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; GFX10-LABEL: temporal_divergent_i32_multiple_use:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_mov_b32 s5, -1
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; GFX10-NEXT: s_mov_b32 s4, 0
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; GFX10-NEXT: .LBB1_1: ; %loop
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; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-NEXT: s_add_i32 s5, s5, 1
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; GFX10-NEXT: v_cvt_f32_u32_e32 v5, s5
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; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v0
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; GFX10-NEXT: v_mov_b32_e32 v5, s5
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; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4
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; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: s_cbranch_execnz .LBB1_1
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; GFX10-NEXT: ; %bb.2: ; %exit
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: flat_store_dword v[1:2], v5
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; GFX10-NEXT: flat_store_dword v[3:4], v5
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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br label %loop
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loop:
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%counter = phi i32 [ 0, %entry ], [ %counter.plus.1, %loop ]
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%f.counter = uitofp i32 %counter to float
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%cond = fcmp ogt float %f.counter, %val
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%counter.plus.1 = add i32 %counter, 1
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br i1 %cond, label %exit, label %loop
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exit:
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store i32 %counter, ptr %addr
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store i32 %counter, ptr %addr2
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ret void
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}
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