fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
69 lines
4.1 KiB
LLVM
69 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX942 %s
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define amdgpu_ps <2 x half> @flat_atomic_fadd_v2f16_rtn(ptr %ptr, <2 x half> %data) {
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; GFX942-LABEL: name: flat_atomic_fadd_v2f16_rtn
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; GFX942: bb.1 (%ir-block.0):
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; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX942-NEXT: {{ $}}
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; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX942-NEXT: [[FLAT_ATOMIC_PK_ADD_F16_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_PK_ADD_F16_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)
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; GFX942-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_PK_ADD_F16_RTN]]
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; GFX942-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
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%ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !0
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ret <2 x half> %ret
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}
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define amdgpu_ps <2 x half> @flat_atomic_fadd_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %data) {
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; GFX942-LABEL: name: flat_atomic_fadd_v2f16_saddr_rtn
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; GFX942: bb.1 (%ir-block.0):
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; GFX942-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0
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; GFX942-NEXT: {{ $}}
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; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX942-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]
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; GFX942-NEXT: [[FLAT_ATOMIC_PK_ADD_F16_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_PK_ADD_F16_RTN [[COPY3]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)
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; GFX942-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_PK_ADD_F16_RTN]]
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; GFX942-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
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%ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !0
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ret <2 x half> %ret
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}
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define amdgpu_ps void @flat_atomic_fadd_v2f16_no_rtn(ptr %ptr, <2 x half> %data) {
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; GFX942-LABEL: name: flat_atomic_fadd_v2f16_no_rtn
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; GFX942: bb.1 (%ir-block.0):
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; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX942-NEXT: {{ $}}
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; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX942-NEXT: FLAT_ATOMIC_PK_ADD_F16 [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)
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; GFX942-NEXT: S_ENDPGM 0
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%ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !0
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ret void
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}
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define amdgpu_ps void @flat_atomic_fadd_v2f16_saddr_no_rtn(ptr inreg %ptr, <2 x half> %data) {
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; GFX942-LABEL: name: flat_atomic_fadd_v2f16_saddr_no_rtn
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; GFX942: bb.1 (%ir-block.0):
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; GFX942-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0
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; GFX942-NEXT: {{ $}}
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; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX942-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]
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; GFX942-NEXT: FLAT_ATOMIC_PK_ADD_F16 [[COPY3]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)
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; GFX942-NEXT: S_ENDPGM 0
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%ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !0
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ret void
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}
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!0 = !{}
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