fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
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define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) {
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; GFX10-LABEL: test_wave32:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dword s0, s[8:9], 0x0
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; GFX10-NEXT: s_load_dword s1, s[8:9], 0x24
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_cmp_eq_u32 s0, 0
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; GFX10-NEXT: s_cselect_b32 s0, 1, 0
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; GFX10-NEXT: s_and_b32 s0, 1, s0
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; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
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; GFX10-NEXT: s_or_b32 s0, s0, s1
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: global_store_dword v[0:1], v0, off
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test_wave32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0
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; GFX11-NEXT: s_load_b32 s1, s[4:5], 0x24
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_cmp_eq_u32 s0, 0
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; GFX11-NEXT: s_cselect_b32 s0, 1, 0
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; GFX11-NEXT: s_and_b32 s0, 1, s0
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; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
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; GFX11-NEXT: s_or_b32 s0, s0, s1
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; GFX11-NEXT: v_mov_b32_e32 v0, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc
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; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX11-NEXT: s_endpgm
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entry:
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%cond = icmp eq i32 %arg0, 0
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%break = call i32 @llvm.amdgcn.if.break.i32(i1 %cond, i32 %saved)
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store volatile i32 %break, ptr addrspace(1) poison
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ret void
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}
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declare i32 @llvm.amdgcn.if.break.i32(i1, i32)
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