1ebfe9b264
AArch64TargetParser reuses data structures and some data from ARMTargetParser, which causes more problems than it solves. This change separates them. Code which is common to ARM and AArch64 is moved to ARMTargetParserCommon which both ARMTargetParser and AArch64TargetParser use. Some of the information in AArch64TargetParser.def was unused or nonsensical (CPU_ATTR, ARCH_ATTR, ARCH_FPU) because it reused data strutures from ARMTargetParser where some of these make sense. These are removed. Differential Revision: https://reviews.llvm.org/D137924
625 lines
18 KiB
C++
625 lines
18 KiB
C++
//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise ARM hardware features
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// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ARMTargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/ARMTargetParserCommon.h"
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#include <cctype>
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using namespace llvm;
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static StringRef getHWDivSynonym(StringRef HWDiv) {
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return StringSwitch<StringRef>(HWDiv)
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.Case("thumb,arm", "arm,thumb")
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.Default(HWDiv);
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}
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// Allows partial match, ex. "v7a" matches "armv7a".
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ARM::ArchKind ARM::parseArch(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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StringRef Syn = getArchSynonym(Arch);
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for (const auto &A : ARCHNames) {
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if (A.getName().endswith(Syn))
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return A.ID;
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}
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return ArchKind::INVALID;
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}
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// Version number (ex. v7 = 7).
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unsigned ARM::parseArchVersion(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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switch (parseArch(Arch)) {
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case ArchKind::ARMV4:
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case ArchKind::ARMV4T:
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return 4;
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case ArchKind::ARMV5T:
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case ArchKind::ARMV5TE:
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case ArchKind::IWMMXT:
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case ArchKind::IWMMXT2:
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case ArchKind::XSCALE:
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case ArchKind::ARMV5TEJ:
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return 5;
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case ArchKind::ARMV6:
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case ArchKind::ARMV6K:
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case ArchKind::ARMV6T2:
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case ArchKind::ARMV6KZ:
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case ArchKind::ARMV6M:
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return 6;
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case ArchKind::ARMV7A:
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case ArchKind::ARMV7VE:
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case ArchKind::ARMV7R:
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case ArchKind::ARMV7M:
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case ArchKind::ARMV7S:
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case ArchKind::ARMV7EM:
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case ArchKind::ARMV7K:
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return 7;
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case ArchKind::ARMV8A:
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case ArchKind::ARMV8_1A:
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case ArchKind::ARMV8_2A:
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case ArchKind::ARMV8_3A:
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case ArchKind::ARMV8_4A:
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case ArchKind::ARMV8_5A:
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case ArchKind::ARMV8_6A:
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case ArchKind::ARMV8_7A:
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case ArchKind::ARMV8_8A:
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case ArchKind::ARMV8R:
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case ArchKind::ARMV8MBaseline:
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case ArchKind::ARMV8MMainline:
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case ArchKind::ARMV8_1MMainline:
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return 8;
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case ArchKind::ARMV9A:
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case ArchKind::ARMV9_1A:
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case ArchKind::ARMV9_2A:
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case ArchKind::ARMV9_3A:
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return 9;
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case ArchKind::INVALID:
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return 0;
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}
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llvm_unreachable("Unhandled architecture");
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}
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static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) {
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switch (AK) {
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case ARM::ArchKind::ARMV6M:
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case ARM::ArchKind::ARMV7M:
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case ARM::ArchKind::ARMV7EM:
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case ARM::ArchKind::ARMV8MMainline:
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case ARM::ArchKind::ARMV8MBaseline:
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case ARM::ArchKind::ARMV8_1MMainline:
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return ARM::ProfileKind::M;
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case ARM::ArchKind::ARMV7R:
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case ARM::ArchKind::ARMV8R:
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return ARM::ProfileKind::R;
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case ARM::ArchKind::ARMV7A:
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case ARM::ArchKind::ARMV7VE:
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case ARM::ArchKind::ARMV7K:
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case ARM::ArchKind::ARMV8A:
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case ARM::ArchKind::ARMV8_1A:
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case ARM::ArchKind::ARMV8_2A:
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case ARM::ArchKind::ARMV8_3A:
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case ARM::ArchKind::ARMV8_4A:
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case ARM::ArchKind::ARMV8_5A:
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case ARM::ArchKind::ARMV8_6A:
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case ARM::ArchKind::ARMV8_7A:
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case ARM::ArchKind::ARMV8_8A:
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case ARM::ArchKind::ARMV9A:
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case ARM::ArchKind::ARMV9_1A:
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case ARM::ArchKind::ARMV9_2A:
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case ARM::ArchKind::ARMV9_3A:
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return ARM::ProfileKind::A;
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case ARM::ArchKind::ARMV4:
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case ARM::ArchKind::ARMV4T:
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case ARM::ArchKind::ARMV5T:
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case ARM::ArchKind::ARMV5TE:
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case ARM::ArchKind::ARMV5TEJ:
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case ARM::ArchKind::ARMV6:
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case ARM::ArchKind::ARMV6K:
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case ARM::ArchKind::ARMV6T2:
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case ARM::ArchKind::ARMV6KZ:
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case ARM::ArchKind::ARMV7S:
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case ARM::ArchKind::IWMMXT:
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case ARM::ArchKind::IWMMXT2:
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case ARM::ArchKind::XSCALE:
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case ARM::ArchKind::INVALID:
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return ARM::ProfileKind::INVALID;
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}
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llvm_unreachable("Unhandled architecture");
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}
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// Profile A/R/M
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ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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return getProfileKind(parseArch(Arch));
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}
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bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
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if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
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return false;
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static const struct FPUFeatureNameInfo {
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const char *PlusName, *MinusName;
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FPUVersion MinVersion;
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FPURestriction MaxRestriction;
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} FPUFeatureInfoList[] = {
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// We have to specify the + and - versions of the name in full so
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// that we can return them as static StringRefs.
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//
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// Also, the SubtargetFeatures ending in just "sp" are listed here
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// under FPURestriction::None, which is the only FPURestriction in
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// which they would be valid (since FPURestriction::SP doesn't
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// exist).
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{"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
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{"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
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{"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
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{"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
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{"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
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{"+vfp3sp", "-vfp3sp", FPUVersion::VFPV3, FPURestriction::None},
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{"+fp16", "-fp16", FPUVersion::VFPV3_FP16, FPURestriction::SP_D16},
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{"+vfp4", "-vfp4", FPUVersion::VFPV4, FPURestriction::None},
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{"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16},
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{"+vfp4d16sp", "-vfp4d16sp", FPUVersion::VFPV4, FPURestriction::SP_D16},
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{"+vfp4sp", "-vfp4sp", FPUVersion::VFPV4, FPURestriction::None},
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{"+fp-armv8", "-fp-armv8", FPUVersion::VFPV5, FPURestriction::None},
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{"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16},
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{"+fp-armv8d16sp", "-fp-armv8d16sp", FPUVersion::VFPV5, FPURestriction::SP_D16},
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{"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
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{"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
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{"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
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{"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
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};
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for (const auto &Info: FPUFeatureInfoList) {
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if (FPUNames[FPUKind].FPUVer >= Info.MinVersion &&
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FPUNames[FPUKind].Restriction <= Info.MaxRestriction)
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Features.push_back(Info.PlusName);
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else
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Features.push_back(Info.MinusName);
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}
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static const struct NeonFeatureNameInfo {
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const char *PlusName, *MinusName;
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NeonSupportLevel MinSupportLevel;
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} NeonFeatureInfoList[] = {
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{"+neon", "-neon", NeonSupportLevel::Neon},
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{"+sha2", "-sha2", NeonSupportLevel::Crypto},
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{"+aes", "-aes", NeonSupportLevel::Crypto},
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};
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for (const auto &Info: NeonFeatureInfoList) {
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if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel)
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Features.push_back(Info.PlusName);
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else
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Features.push_back(Info.MinusName);
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}
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return true;
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}
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// Little/Big endian
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ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
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if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
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Arch.startswith("aarch64_be"))
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return EndianKind::BIG;
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if (Arch.startswith("arm") || Arch.startswith("thumb")) {
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if (Arch.endswith("eb"))
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return EndianKind::BIG;
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else
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return EndianKind::LITTLE;
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}
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if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
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return EndianKind::LITTLE;
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return EndianKind::INVALID;
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}
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// ARM, Thumb, AArch64
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ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
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return StringSwitch<ISAKind>(Arch)
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.StartsWith("aarch64", ISAKind::AARCH64)
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.StartsWith("arm64", ISAKind::AARCH64)
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.StartsWith("thumb", ISAKind::THUMB)
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.StartsWith("arm", ISAKind::ARM)
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.Default(ISAKind::INVALID);
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}
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unsigned ARM::parseFPU(StringRef FPU) {
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StringRef Syn = getFPUSynonym(FPU);
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for (const auto &F : FPUNames) {
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if (Syn == F.getName())
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return F.ID;
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}
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return FK_INVALID;
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}
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ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return NeonSupportLevel::None;
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return FPUNames[FPUKind].NeonSupport;
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}
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StringRef ARM::getFPUSynonym(StringRef FPU) {
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return StringSwitch<StringRef>(FPU)
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.Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
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.Case("vfp2", "vfpv2")
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.Case("vfp3", "vfpv3")
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.Case("vfp4", "vfpv4")
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.Case("vfp3-d16", "vfpv3-d16")
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.Case("vfp4-d16", "vfpv4-d16")
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.Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
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.Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
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.Case("fp5-sp-d16", "fpv5-sp-d16")
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.Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
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// FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
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.Case("neon-vfpv3", "neon")
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.Default(FPU);
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}
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StringRef ARM::getFPUName(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return StringRef();
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return FPUNames[FPUKind].getName();
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}
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ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return FPUVersion::NONE;
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return FPUNames[FPUKind].FPUVer;
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}
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ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return FPURestriction::None;
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return FPUNames[FPUKind].Restriction;
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}
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unsigned ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
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if (CPU == "generic")
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return ARM::ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
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return StringSwitch<unsigned>(CPU)
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, DEFAULT_FPU)
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#include "llvm/Support/ARMTargetParser.def"
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.Default(ARM::FK_INVALID);
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}
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uint64_t ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
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if (CPU == "generic")
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return ARM::ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
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return StringSwitch<uint64_t>(CPU)
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, \
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ARCHNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
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DEFAULT_EXT)
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#include "llvm/Support/ARMTargetParser.def"
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.Default(ARM::AEK_INVALID);
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}
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bool ARM::getHWDivFeatures(uint64_t HWDivKind,
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std::vector<StringRef> &Features) {
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if (HWDivKind == AEK_INVALID)
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return false;
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if (HWDivKind & AEK_HWDIVARM)
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Features.push_back("+hwdiv-arm");
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else
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Features.push_back("-hwdiv-arm");
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if (HWDivKind & AEK_HWDIVTHUMB)
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Features.push_back("+hwdiv");
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else
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Features.push_back("-hwdiv");
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return true;
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}
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bool ARM::getExtensionFeatures(uint64_t Extensions,
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std::vector<StringRef> &Features) {
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if (Extensions == AEK_INVALID)
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return false;
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for (const auto &AE : ARCHExtNames) {
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if ((Extensions & AE.ID) == AE.ID && AE.Feature)
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Features.push_back(AE.Feature);
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else if (AE.NegFeature)
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Features.push_back(AE.NegFeature);
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}
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return getHWDivFeatures(Extensions, Features);
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}
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StringRef ARM::getArchName(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getName();
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}
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StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
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}
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StringRef ARM::getSubArch(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getSubArch();
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}
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unsigned ARM::getArchAttr(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
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}
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StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
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for (const auto &AE : ARCHExtNames) {
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if (ArchExtKind == AE.ID)
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return AE.getName();
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}
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return StringRef();
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}
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static bool stripNegationPrefix(StringRef &Name) {
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if (Name.startswith("no")) {
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Name = Name.substr(2);
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return true;
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}
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return false;
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}
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StringRef ARM::getArchExtFeature(StringRef ArchExt) {
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bool Negated = stripNegationPrefix(ArchExt);
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for (const auto &AE : ARCHExtNames) {
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if (AE.Feature && ArchExt == AE.getName())
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return StringRef(Negated ? AE.NegFeature : AE.Feature);
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}
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return StringRef();
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}
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static unsigned findDoublePrecisionFPU(unsigned InputFPUKind) {
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const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
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// If the input FPU already supports double-precision, then there
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// isn't any different FPU we can return here.
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//
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// The current available FPURestriction values are None (no
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// restriction), D16 (only 16 d-regs) and SP_D16 (16 d-regs
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// and single precision only); there's no value representing
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// SP restriction without D16. So this test just means 'is it
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// SP only?'.
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if (InputFPU.Restriction != ARM::FPURestriction::SP_D16)
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return ARM::FK_INVALID;
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// Otherwise, look for an FPU entry with all the same fields, except
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// that SP_D16 has been replaced with just D16, representing adding
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// double precision and not changing anything else.
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for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
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if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
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CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
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CandidateFPU.Restriction == ARM::FPURestriction::D16) {
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return CandidateFPU.ID;
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}
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}
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// nothing found
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return ARM::FK_INVALID;
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}
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bool ARM::appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
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StringRef ArchExt,
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std::vector<StringRef> &Features,
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unsigned &ArgFPUID) {
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size_t StartingNumFeatures = Features.size();
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const bool Negated = stripNegationPrefix(ArchExt);
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uint64_t ID = parseArchExt(ArchExt);
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if (ID == AEK_INVALID)
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return false;
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for (const auto &AE : ARCHExtNames) {
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if (Negated) {
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if ((AE.ID & ID) == ID && AE.NegFeature)
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Features.push_back(AE.NegFeature);
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} else {
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if ((AE.ID & ID) == AE.ID && AE.Feature)
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Features.push_back(AE.Feature);
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}
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}
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if (CPU == "")
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CPU = "generic";
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if (ArchExt == "fp" || ArchExt == "fp.dp") {
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unsigned FPUKind;
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if (ArchExt == "fp.dp") {
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if (Negated) {
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Features.push_back("-fp64");
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return true;
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}
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FPUKind = findDoublePrecisionFPU(getDefaultFPU(CPU, AK));
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} else if (Negated) {
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FPUKind = ARM::FK_NONE;
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} else {
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FPUKind = getDefaultFPU(CPU, AK);
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}
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ArgFPUID = FPUKind;
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return ARM::getFPUFeatures(FPUKind, Features);
|
|
}
|
|
return StartingNumFeatures != Features.size();
|
|
}
|
|
|
|
ARM::ArchKind ARM::convertV9toV8(ARM::ArchKind AK) {
|
|
if (getProfileKind(AK) != ProfileKind::A)
|
|
return ARM::ArchKind::INVALID;
|
|
if (AK < ARM::ArchKind::ARMV9A || AK > ARM::ArchKind::ARMV9_3A)
|
|
return ARM::ArchKind::INVALID;
|
|
unsigned AK_v8 = static_cast<unsigned>(ARM::ArchKind::ARMV8_5A);
|
|
AK_v8 += static_cast<unsigned>(AK) -
|
|
static_cast<unsigned>(ARM::ArchKind::ARMV9A);
|
|
return static_cast<ARM::ArchKind>(AK_v8);
|
|
}
|
|
|
|
StringRef ARM::getDefaultCPU(StringRef Arch) {
|
|
ArchKind AK = parseArch(Arch);
|
|
if (AK == ArchKind::INVALID)
|
|
return StringRef();
|
|
|
|
// Look for multiple AKs to find the default for pair AK+Name.
|
|
for (const auto &CPU : CPUNames) {
|
|
if (CPU.ArchID == AK && CPU.Default)
|
|
return CPU.getName();
|
|
}
|
|
|
|
// If we can't find a default then target the architecture instead
|
|
return "generic";
|
|
}
|
|
|
|
uint64_t ARM::parseHWDiv(StringRef HWDiv) {
|
|
StringRef Syn = getHWDivSynonym(HWDiv);
|
|
for (const auto &D : HWDivNames) {
|
|
if (Syn == D.getName())
|
|
return D.ID;
|
|
}
|
|
return AEK_INVALID;
|
|
}
|
|
|
|
uint64_t ARM::parseArchExt(StringRef ArchExt) {
|
|
for (const auto &A : ARCHExtNames) {
|
|
if (ArchExt == A.getName())
|
|
return A.ID;
|
|
}
|
|
return AEK_INVALID;
|
|
}
|
|
|
|
ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
|
|
for (const auto &C : CPUNames) {
|
|
if (CPU == C.getName())
|
|
return C.ArchID;
|
|
}
|
|
return ArchKind::INVALID;
|
|
}
|
|
|
|
void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
|
|
for (const CpuNames<ArchKind> &Arch : CPUNames) {
|
|
if (Arch.ArchID != ArchKind::INVALID)
|
|
Values.push_back(Arch.getName());
|
|
}
|
|
}
|
|
|
|
StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
|
|
StringRef ArchName =
|
|
CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU));
|
|
|
|
if (TT.isOSBinFormatMachO()) {
|
|
if (TT.getEnvironment() == Triple::EABI ||
|
|
TT.getOS() == Triple::UnknownOS ||
|
|
parseArchProfile(ArchName) == ProfileKind::M)
|
|
return "aapcs";
|
|
if (TT.isWatchABI())
|
|
return "aapcs16";
|
|
return "apcs-gnu";
|
|
} else if (TT.isOSWindows())
|
|
// FIXME: this is invalid for WindowsCE.
|
|
return "aapcs";
|
|
|
|
// Select the default based on the platform.
|
|
switch (TT.getEnvironment()) {
|
|
case Triple::Android:
|
|
case Triple::GNUEABI:
|
|
case Triple::GNUEABIHF:
|
|
case Triple::MuslEABI:
|
|
case Triple::MuslEABIHF:
|
|
return "aapcs-linux";
|
|
case Triple::EABIHF:
|
|
case Triple::EABI:
|
|
return "aapcs";
|
|
default:
|
|
if (TT.isOSNetBSD())
|
|
return "apcs-gnu";
|
|
if (TT.isOSOpenBSD())
|
|
return "aapcs-linux";
|
|
return "aapcs";
|
|
}
|
|
}
|
|
|
|
StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
|
|
if (MArch.empty())
|
|
MArch = Triple.getArchName();
|
|
MArch = llvm::ARM::getCanonicalArchName(MArch);
|
|
|
|
// Some defaults are forced.
|
|
switch (Triple.getOS()) {
|
|
case llvm::Triple::FreeBSD:
|
|
case llvm::Triple::NetBSD:
|
|
case llvm::Triple::OpenBSD:
|
|
if (!MArch.empty() && MArch == "v6")
|
|
return "arm1176jzf-s";
|
|
if (!MArch.empty() && MArch == "v7")
|
|
return "cortex-a8";
|
|
break;
|
|
case llvm::Triple::Win32:
|
|
// FIXME: this is invalid for WindowsCE
|
|
if (llvm::ARM::parseArchVersion(MArch) <= 7)
|
|
return "cortex-a9";
|
|
break;
|
|
case llvm::Triple::IOS:
|
|
case llvm::Triple::MacOSX:
|
|
case llvm::Triple::TvOS:
|
|
case llvm::Triple::WatchOS:
|
|
case llvm::Triple::DriverKit:
|
|
if (MArch == "v7k")
|
|
return "cortex-a7";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (MArch.empty())
|
|
return StringRef();
|
|
|
|
StringRef CPU = llvm::ARM::getDefaultCPU(MArch);
|
|
if (!CPU.empty() && !CPU.equals("invalid"))
|
|
return CPU;
|
|
|
|
// If no specific architecture version is requested, return the minimum CPU
|
|
// required by the OS and environment.
|
|
switch (Triple.getOS()) {
|
|
case llvm::Triple::NetBSD:
|
|
switch (Triple.getEnvironment()) {
|
|
case llvm::Triple::EABI:
|
|
case llvm::Triple::EABIHF:
|
|
case llvm::Triple::GNUEABI:
|
|
case llvm::Triple::GNUEABIHF:
|
|
return "arm926ej-s";
|
|
default:
|
|
return "strongarm";
|
|
}
|
|
case llvm::Triple::NaCl:
|
|
case llvm::Triple::OpenBSD:
|
|
return "cortex-a8";
|
|
default:
|
|
switch (Triple.getEnvironment()) {
|
|
case llvm::Triple::EABIHF:
|
|
case llvm::Triple::GNUEABIHF:
|
|
case llvm::Triple::MuslEABIHF:
|
|
return "arm1176jzf-s";
|
|
default:
|
|
return "arm7tdmi";
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("invalid arch name");
|
|
}
|