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llvm-project/llvm/lib/Target/RISCV
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Michael Maitland 2323a4ee61 Revert "[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV" 
This reverts commit 5e82ee5373211db8522181054800ccd49461d9d8.
2022-11-15 08:04:11 -08:00
..
AsmParser
[RISCV][CodeGen] add assertion to RISCVTargetStreamer getTargetStreamer()
2022-08-31 11:15:47 -07:00
Disassembler
[RISCV] Implement assembler support for XVentanaCondOps
2022-11-14 09:01:54 -08:00
MCTargetDesc
[NFC][RISCV] Move getSEWLMULRatio function to header
2022-10-05 15:10:53 +01:00
TargetInfo
[RISCV] Re-enable JIT support
2022-08-11 11:41:02 +02:00
CMakeLists.txt
Revert "[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV"
2022-11-15 08:04:11 -08:00
RISCV.h
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCV.td
[RISCV] Implement assembler support for XVentanaCondOps
2022-11-14 09:01:54 -08:00
RISCVAsmPrinter.cpp
[RISC-V][HWASAN] Fold variable into assert
2022-08-29 00:32:37 +02:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
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RISCVCallLowering.h
…
RISCVCodeGenPrepare.cpp
[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add basic support for the sifive-7-series short forward branch optimization.
2022-10-17 13:56:22 -07:00
RISCVFrameLowering.cpp
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
RISCVFrameLowering.h
Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"
2022-11-01 20:04:07 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Extend strided load/store pattern matching to non-loop cases
2022-09-27 12:56:58 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Map pseudos to their BaseInstr to reduce cases
2022-10-27 16:50:15 +08:00
RISCVInstrFormats.td
[RISCV] Define custom-N opcodes
2022-11-04 10:05:30 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Use OPCFG format record for vsetvli in tablgen. NFC
2022-11-10 21:08:07 -08:00
RISCVInstrInfo.cpp
[MachineCombiner][RISCV] Enable MachineCombiner for RISCV
2022-10-18 18:56:32 +03:00
RISCVInstrInfo.h
[MachineCombiner][RISCV] Enable MachineCombiner for RISCV
2022-10-18 18:56:32 +03:00
RISCVInstrInfo.td
[RISCV] Implement assembler support for XVentanaCondOps
2022-11-14 09:01:54 -08:00
RISCVInstrInfoA.td
[RISCV] Add target feature to force-enable atomics
2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td
[RISCV] : Add support for simm10_lsb0000nonzero operand.
2022-08-26 14:37:37 +08:00
RISCVInstrInfoD.td
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
RISCVInstrInfoF.td
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
RISCVInstrInfoM.td
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td
[RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
2022-11-03 09:18:42 -07:00
RISCVInstrInfoVPseudos.td
Revert "[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV"
2022-11-15 08:04:11 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber.
2022-10-03 21:44:08 -07:00
RISCVInstrInfoVVLPatterns.td
[VP][RISCV] Add vp.rint and RISC-V support.
2022-11-01 14:52:47 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Implement assembler support for XVentanaCondOps
2022-11-14 09:01:54 -08:00
RISCVInstrInfoZb.td
[RISCV] Expand i32 abs to negw+max at isel.
2022-11-14 19:44:05 -08:00
RISCVInstrInfoZfh.td
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Add PACKH/PACKW/PACK to hasAllNBitUsers.
2022-11-13 23:57:52 -08:00
RISCVISelDAGToDAG.h
[RISCV] Improve selection of PACK/PACKW for AssertZExt input.
2022-11-13 16:00:45 -08:00
RISCVISelLowering.cpp
[RISCV] Teach shouldSinkOperands that vp.add and friends are commutative.
2022-11-14 22:01:59 -08:00
RISCVISelLowering.h
[RISCV] Expand i32 abs to negw+max at isel.
2022-11-14 19:44:05 -08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.cpp
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMacroFusion.cpp
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Fix wrong register rename for store value during make-compressible optimization
2022-07-08 18:07:17 +08:00
RISCVMCInstLower.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVMergeBaseOffset.cpp
[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.
2022-08-02 15:27:23 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
2022-08-29 09:05:53 -07:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"
2022-11-01 20:04:07 -07:00
RISCVRegisterInfo.h
Revert "[RISCV] Enable the LocalStackSlotAllocation pass support"
2022-11-01 20:04:07 -07:00
RISCVRegisterInfo.td
[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
2022-08-24 14:16:20 +00:00
RISCVSchedRocket.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedule.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVScheduleV.td
[RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
2022-11-03 09:18:42 -07:00
RISCVScheduleZb.td
[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
2022-09-23 21:38:42 -07:00
RISCVSExtWRemoval.cpp
[RISCV] Add PseudoCCMOVGPR to RISCVSExtWRemoval.
2022-11-14 13:39:00 -08:00
RISCVSubtarget.cpp
[RISCV] Enable fixed length vectors and loop vectorization with same
2022-08-26 14:45:23 -07:00
RISCVSubtarget.h
[RISCV] Implement assembler support for XVentanaCondOps
2022-11-14 09:01:54 -08:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
[RISCV] Adjust RV64I data layout by using n32:64 in layout string
2022-10-28 08:27:03 -07:00
RISCVTargetMachine.h
[llvm] Remove redundaunt virtual specifiers (NFC)
2022-07-24 21:50:35 -07:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Prevent autovectorization using vscale with Zvl32b.
2022-11-02 13:55:21 -07:00
RISCVTargetTransformInfo.h
[LV][RISCV] Disable vectorization of epilogue loops
2022-10-25 14:28:02 -07:00