1e7c1dd67c
This bug was introduced with D136713 / 54eeadcf442df91aed0 . As an enhancement, we could cast operands to the expected type, but we need to make sure that is done correctly (zext vs. sext). It's also possible (but seems unlikely) that an operand can have a type larger than the result type. Fixes #58661
319 lines
10 KiB
LLVM
319 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
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; Verify that we correctly fold target specific packed vector shifts by
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; immediate count into a simple build_vector when the elements of the vector
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; in input to the packed shift are all constants or undef.
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define <8 x i16> @test1() {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [8,16,32,64,8,16,32,64]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> <i16 1, i16 2, i16 4, i16 8, i16 1, i16 2, i16 4, i16 8>, i32 3)
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ret <8 x i16> %1
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}
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define <8 x i16> @test2() {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4,0,1,2,4]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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define <8 x i16> @test3() {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4,0,1,2,4]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test4() {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [8,16,32,64]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 1, i32 2, i32 4, i32 8>, i32 3)
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ret <4 x i32> %1
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}
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define <4 x i32> @test5() {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <4 x i32> @test6() {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,1,2,4]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <2 x i64> @test7() {
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; X86-LABEL: test7:
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; X86: # %bb.0:
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; X86-NEXT: movaps {{.*#+}} xmm0 = [8,0,16,0]
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; X86-NEXT: retl
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;
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; X64-LABEL: test7:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [8,16]
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 1, i64 2>, i32 3)
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ret <2 x i64> %1
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}
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define <2 x i64> @test8() {
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; X86-LABEL: test8:
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; X86: # %bb.0:
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; X86-NEXT: movaps {{.*#+}} xmm0 = [1,0,2,0]
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; X86-NEXT: retl
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;
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; X64-LABEL: test8:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [1,2]
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 8, i64 16>, i32 3)
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ret <2 x i64> %1
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}
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define <8 x i16> @test9() {
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; CHECK-LABEL: test9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test10() {
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; CHECK-LABEL: test10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,1,0,4]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <2 x i64> @test11() {
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; X86-LABEL: test11:
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; X86: # %bb.0:
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; X86-NEXT: movaps {{.*#+}} xmm0 = [0,0,3,0]
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; X86-NEXT: retl
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;
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; X64-LABEL: test11:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0]
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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define <8 x i16> @test12() {
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; CHECK-LABEL: test12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test13() {
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; CHECK-LABEL: test13:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,1,0,4]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <8 x i16> @test14() {
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; CHECK-LABEL: test14:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1,1,0,0,3,0,8,16]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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define <4 x i32> @test15() {
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; CHECK-LABEL: test15:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,64,0,256]
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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define <2 x i64> @test16() {
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; X86-LABEL: test16:
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; X86: # %bb.0:
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; X86-NEXT: movaps {{.*#+}} xmm0 = [0,0,248,0]
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; X86-NEXT: retl
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;
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; X64-LABEL: test16:
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; X64: # %bb.0:
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; X64-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,248,0,0,0,0,0,0,0]
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; X64-NEXT: retq
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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; Make sure we fold fully undef input vectors. We previously folded only when
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; undef had a single use so use 2 undefs.
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define <4 x i32> @test17(<4 x i32> %a0, ptr %dummy) {
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; X86-LABEL: test17:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorps %xmm0, %xmm0
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; X86-NEXT: movaps %xmm0, (%eax)
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; X86-NEXT: xorps %xmm0, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test17:
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; X64: # %bb.0:
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: movaps %xmm0, (%rdi)
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: retq
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%a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 6)
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store <4 x i32> %a, ptr %dummy
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%res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 7)
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ret <4 x i32> %res
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}
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define <4 x i32> @test18(<4 x i32> %a0, ptr %dummy) {
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; X86-LABEL: test18:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorps %xmm0, %xmm0
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; X86-NEXT: movaps %xmm0, (%eax)
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; X86-NEXT: xorps %xmm0, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test18:
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; X64: # %bb.0:
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: movaps %xmm0, (%rdi)
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: retq
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%a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 3)
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store <4 x i32> %a, ptr %dummy
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%res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 1)
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ret <4 x i32> %res
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}
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; PR39482
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define <4 x i32> @extelt0_sub_pslli_v4i32(<4 x i32> %x, <4 x i32> %y){
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; CHECK-LABEL: extelt0_sub_pslli_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32]
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; CHECK-NEXT: psubd %xmm1, %xmm2
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
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; CHECK-NEXT: pslld %xmm1, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%ext = extractelement <4 x i32> %y, i64 0
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%bo = sub i32 32, %ext
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%r = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %x, i32 %bo)
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ret <4 x i32> %r
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}
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define <4 x i32> @extelt1_add_psrli_v4i32(<4 x i32> %x, <4 x i32> %y){
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; X86-LABEL: extelt1_add_psrli_v4i32:
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; X86: # %bb.0:
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; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
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; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
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; X86-NEXT: xorps %xmm2, %xmm2
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; X86-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X86-NEXT: psrld %xmm2, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: extelt1_add_psrli_v4i32:
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; X64: # %bb.0:
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
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; X64-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; X64-NEXT: xorps %xmm2, %xmm2
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; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X64-NEXT: psrld %xmm2, %xmm0
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; X64-NEXT: retq
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%ext = extractelement <4 x i32> %y, i64 1
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%bo = add i32 %ext, 3
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%r = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %x, i32 %bo)
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ret <4 x i32> %r
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}
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define i32 @extelt1_add_psrai_v4i32_uses(<4 x i32> %x, <4 x i32> %y){
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; CHECK-LABEL: extelt1_add_psrai_v4i32_uses:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
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; CHECK-NEXT: movd %xmm1, %ecx
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; CHECK-NEXT: addl $3, %ecx
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; CHECK-NEXT: movd %ecx, %xmm1
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; CHECK-NEXT: psrad %xmm1, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
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; CHECK-NEXT: movd %xmm0, %eax
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; CHECK-NEXT: imull %ecx, %eax
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; CHECK-NEXT: ret{{[l|q]}}
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%ext = extractelement <4 x i32> %y, i64 1
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%bo = add i32 %ext, 3
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%r = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %x, i32 %bo)
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%ext3 = extractelement <4 x i32> %r, i64 3
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%r2 = mul i32 %bo, %ext3
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ret i32 %r2
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}
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define <4 x i32> @extelt0_twice_sub_pslli_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z){
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; CHECK-LABEL: extelt0_twice_sub_pslli_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movd %xmm1, %eax
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; CHECK-NEXT: movd %xmm2, %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: movd %eax, %xmm1
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; CHECK-NEXT: pslld %xmm1, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%ext1 = extractelement <4 x i32> %y, i64 0
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%ext2 = extractelement <4 x i32> %z, i64 0
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%bo = sub i32 %ext1, %ext2
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%r = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %x, i32 %bo)
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ret <4 x i32> %r
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}
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; This would crash because the scalar shift amount has a different type than the shift result.
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define <2 x i8> @PR58661(<2 x i8> %a0) {
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; CHECK-LABEL: PR58661:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrlw $8, %xmm0
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; CHECK-NEXT: movd %xmm0, %eax
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; CHECK-NEXT: shll $8, %eax
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; CHECK-NEXT: movd %eax, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%shuffle = shufflevector <2 x i8> %a0, <2 x i8> <i8 poison, i8 0>, <2 x i32> <i32 1, i32 3>
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%x = bitcast <2 x i8> %shuffle to i16
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%shl = shl nuw i16 %x, 8
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%y = bitcast i16 %shl to <2 x i8>
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ret <2 x i8> %y
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}
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declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
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declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
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declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32)
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declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32)
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