127 lines
4.1 KiB
C++
127 lines
4.1 KiB
C++
//===-- AMDGPUPrepareAGPRAlloc.cpp ----------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Make simple transformations to relax register constraints for cases which can
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// allocate to AGPRs or VGPRs. Replace materialize of inline immediates into
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// AGPR or VGPR with a pseudo with an AV_* class register constraint. This
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// allows later passes to inflate the register class if necessary. The register
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// allocator does not know to replace instructions to relax constraints.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUPrepareAGPRAlloc.h"
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-prepare-agpr-alloc"
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namespace {
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class AMDGPUPrepareAGPRAllocImpl {
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private:
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const SIInstrInfo &TII;
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MachineRegisterInfo &MRI;
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bool isAV64Imm(const MachineOperand &MO) const;
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public:
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AMDGPUPrepareAGPRAllocImpl(const GCNSubtarget &ST, MachineRegisterInfo &MRI)
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: TII(*ST.getInstrInfo()), MRI(MRI) {}
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bool run(MachineFunction &MF);
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};
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class AMDGPUPrepareAGPRAllocLegacy : public MachineFunctionPass {
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public:
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static char ID;
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AMDGPUPrepareAGPRAllocLegacy() : MachineFunctionPass(ID) {
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initializeAMDGPUPrepareAGPRAllocLegacyPass(
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*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "AMDGPU Prepare AGPR Alloc"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(AMDGPUPrepareAGPRAllocLegacy, DEBUG_TYPE,
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"AMDGPU Prepare AGPR Alloc", false, false)
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INITIALIZE_PASS_END(AMDGPUPrepareAGPRAllocLegacy, DEBUG_TYPE,
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"AMDGPU Prepare AGPR Alloc", false, false)
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char AMDGPUPrepareAGPRAllocLegacy::ID = 0;
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char &llvm::AMDGPUPrepareAGPRAllocLegacyID = AMDGPUPrepareAGPRAllocLegacy::ID;
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bool AMDGPUPrepareAGPRAllocLegacy::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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return AMDGPUPrepareAGPRAllocImpl(ST, MF.getRegInfo()).run(MF);
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}
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PreservedAnalyses
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AMDGPUPrepareAGPRAllocPass::run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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AMDGPUPrepareAGPRAllocImpl(ST, MF.getRegInfo()).run(MF);
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return PreservedAnalyses::all();
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}
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bool AMDGPUPrepareAGPRAllocImpl::isAV64Imm(const MachineOperand &MO) const {
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return MO.isImm() && TII.isLegalAV64PseudoImm(MO.getImm());
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}
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bool AMDGPUPrepareAGPRAllocImpl::run(MachineFunction &MF) {
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if (MRI.isReserved(AMDGPU::AGPR0))
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return false;
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const MCInstrDesc &AVImmPseudo32 = TII.get(AMDGPU::AV_MOV_B32_IMM_PSEUDO);
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const MCInstrDesc &AVImmPseudo64 = TII.get(AMDGPU::AV_MOV_B64_IMM_PSEUDO);
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if ((MI.getOpcode() == AMDGPU::V_MOV_B32_e32 &&
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TII.isInlineConstant(MI, 1)) ||
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(MI.getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
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MI.getOperand(1).isImm())) {
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MI.setDesc(AVImmPseudo32);
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Changed = true;
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continue;
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}
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// TODO: If only half of the value is rewritable, is it worth splitting it
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// up?
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if ((MI.getOpcode() == AMDGPU::V_MOV_B64_e64 ||
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MI.getOpcode() == AMDGPU::V_MOV_B64_PSEUDO) &&
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isAV64Imm(MI.getOperand(1))) {
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MI.setDesc(AVImmPseudo64);
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Changed = true;
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continue;
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}
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}
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}
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return Changed;
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}
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