Ron Lieberman 09b53296cf Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" ...

This reverts commit 9075009d1fd5f2bf9aa6c2f362d2993691a316b3.

 Failed amdgpu runtime buildbot # 3514

2021-12-22 11:39:28 -05:00

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custom-pseudo-source-values.ll

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

expected-target-index-name.mir

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intrinsics.mir

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invalid-frame-index2.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-invalid-fixed-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-invalid-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-no-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-target-index-operand.mir

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lit.local.cfg

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llc-target-cpu-attr-from-cmdline-ir.mir

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llc-target-cpu-attr-from-cmdline.mir

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load-store-opt-dlc.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

machine-function-info-after-pei.ll

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

machine-function-info-dynlds-align-invalid-case.mir

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machine-function-info-no-ir.mir

AMDGPU: Enable fixed function ABI by default

2021-12-04 10:49:18 -05:00

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

AMDGPU: Enable fixed function ABI by default

2021-12-04 10:49:18 -05:00

machine-metadata-error.mir

[MIRParser] Add machine metadata.

2021-06-28 22:29:36 -04:00

machine-metadata.mir

Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range"

2021-12-22 11:39:28 -05:00

mfi-frame-offset-reg-class.mir

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mfi-parse-error-frame-offset-reg.mir

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mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

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mfi-scratch-rsrc-reg-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

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mir-canon-multi.mir

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mircanon-memoperands.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

parse-order-reserved-regs.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

stack-id-assert.mir

Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range"

2021-12-22 11:39:28 -05:00

stack-id.mir

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subreg-def-is-not-ssa.mir

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syncscopes.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

target-flags.mir

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target-index-operands.mir

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