a4830d14ed
With VectorType supporting scalable dimensions, we don't need many of
the operations currently present in ArmSVE, like mask generation and
basic arithmetic instructions. Therefore, this patch also gets
rid of those.
Having built-in scalable vector support also simplifies the lowering of
scalable vector dialects down to LLVMIR.
Scalable dimensions are indicated with the scalable dimensions
between square brackets:
vector<[4]xf32>
Is a scalable vector of 4 single precission floating point elements.
More generally, a VectorType can have a set of fixed-length dimensions
followed by a set of scalable dimensions:
vector<2x[4x4]xf32>
Is a vector with 2 scalable 4x4 vectors of single precission floating
point elements.
The scale of the scalable dimensions can be obtained with the Vector
operation:
%vs = vector.vscale
This change is being discussed in the discourse RFC:
https://llvm.discourse.group/t/rfc-add-built-in-support-for-scalable-vector-types/4484
Differential Revision: https://reviews.llvm.org/D111819
139 lines
5.5 KiB
C++
139 lines
5.5 KiB
C++
//===- LegalizeForLLVMExport.cpp - Prepare ArmSVE for LLVM translation ----===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
|
|
#include "mlir/Conversion/LLVMCommon/Pattern.h"
|
|
#include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
|
|
#include "mlir/Dialect/ArmSVE/Transforms.h"
|
|
#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
|
|
#include "mlir/Dialect/StandardOps/IR/Ops.h"
|
|
#include "mlir/IR/BuiltinOps.h"
|
|
#include "mlir/IR/PatternMatch.h"
|
|
|
|
using namespace mlir;
|
|
using namespace mlir::arm_sve;
|
|
|
|
template <typename OpTy>
|
|
class ForwardOperands : public OpConversionPattern<OpTy> {
|
|
using OpConversionPattern<OpTy>::OpConversionPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(OpTy op, typename OpTy::Adaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const final {
|
|
if (adaptor.getOperands().getTypes() == op->getOperands().getTypes())
|
|
return rewriter.notifyMatchFailure(op, "operand types already match");
|
|
|
|
rewriter.updateRootInPlace(
|
|
op, [&]() { op->setOperands(adaptor.getOperands()); });
|
|
return success();
|
|
}
|
|
};
|
|
|
|
class ReturnOpTypeConversion : public OpConversionPattern<ReturnOp> {
|
|
public:
|
|
using OpConversionPattern<ReturnOp>::OpConversionPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(ReturnOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const final {
|
|
rewriter.updateRootInPlace(
|
|
op, [&]() { op->setOperands(adaptor.getOperands()); });
|
|
return success();
|
|
}
|
|
};
|
|
|
|
using SdotOpLowering = OneToOneConvertToLLVMPattern<SdotOp, SdotIntrOp>;
|
|
using SmmlaOpLowering = OneToOneConvertToLLVMPattern<SmmlaOp, SmmlaIntrOp>;
|
|
using UdotOpLowering = OneToOneConvertToLLVMPattern<UdotOp, UdotIntrOp>;
|
|
using UmmlaOpLowering = OneToOneConvertToLLVMPattern<UmmlaOp, UmmlaIntrOp>;
|
|
using ScalableMaskedAddIOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedAddIOp,
|
|
ScalableMaskedAddIIntrOp>;
|
|
using ScalableMaskedAddFOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedAddFOp,
|
|
ScalableMaskedAddFIntrOp>;
|
|
using ScalableMaskedSubIOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedSubIOp,
|
|
ScalableMaskedSubIIntrOp>;
|
|
using ScalableMaskedSubFOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedSubFOp,
|
|
ScalableMaskedSubFIntrOp>;
|
|
using ScalableMaskedMulIOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedMulIOp,
|
|
ScalableMaskedMulIIntrOp>;
|
|
using ScalableMaskedMulFOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedMulFOp,
|
|
ScalableMaskedMulFIntrOp>;
|
|
using ScalableMaskedSDivIOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedSDivIOp,
|
|
ScalableMaskedSDivIIntrOp>;
|
|
using ScalableMaskedUDivIOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedUDivIOp,
|
|
ScalableMaskedUDivIIntrOp>;
|
|
using ScalableMaskedDivFOpLowering =
|
|
OneToOneConvertToLLVMPattern<ScalableMaskedDivFOp,
|
|
ScalableMaskedDivFIntrOp>;
|
|
|
|
/// Populate the given list with patterns that convert from ArmSVE to LLVM.
|
|
void mlir::populateArmSVELegalizeForLLVMExportPatterns(
|
|
LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
|
|
// Populate conversion patterns
|
|
|
|
// clang-format off
|
|
patterns.add<ForwardOperands<CallOp>,
|
|
ForwardOperands<CallIndirectOp>,
|
|
ForwardOperands<ReturnOp>>(converter,
|
|
&converter.getContext());
|
|
patterns.add<SdotOpLowering,
|
|
SmmlaOpLowering,
|
|
UdotOpLowering,
|
|
UmmlaOpLowering,
|
|
ScalableMaskedAddIOpLowering,
|
|
ScalableMaskedAddFOpLowering,
|
|
ScalableMaskedSubIOpLowering,
|
|
ScalableMaskedSubFOpLowering,
|
|
ScalableMaskedMulIOpLowering,
|
|
ScalableMaskedMulFOpLowering,
|
|
ScalableMaskedSDivIOpLowering,
|
|
ScalableMaskedUDivIOpLowering,
|
|
ScalableMaskedDivFOpLowering>(converter);
|
|
// clang-format on
|
|
}
|
|
|
|
void mlir::configureArmSVELegalizeForExportTarget(
|
|
LLVMConversionTarget &target) {
|
|
// clang-format off
|
|
target.addLegalOp<SdotIntrOp,
|
|
SmmlaIntrOp,
|
|
UdotIntrOp,
|
|
UmmlaIntrOp,
|
|
ScalableMaskedAddIIntrOp,
|
|
ScalableMaskedAddFIntrOp,
|
|
ScalableMaskedSubIIntrOp,
|
|
ScalableMaskedSubFIntrOp,
|
|
ScalableMaskedMulIIntrOp,
|
|
ScalableMaskedMulFIntrOp,
|
|
ScalableMaskedSDivIIntrOp,
|
|
ScalableMaskedUDivIIntrOp,
|
|
ScalableMaskedDivFIntrOp>();
|
|
target.addIllegalOp<SdotOp,
|
|
SmmlaOp,
|
|
UdotOp,
|
|
UmmlaOp,
|
|
ScalableMaskedAddIOp,
|
|
ScalableMaskedAddFOp,
|
|
ScalableMaskedSubIOp,
|
|
ScalableMaskedSubFOp,
|
|
ScalableMaskedMulIOp,
|
|
ScalableMaskedMulFOp,
|
|
ScalableMaskedSDivIOp,
|
|
ScalableMaskedUDivIOp,
|
|
ScalableMaskedDivFOp>();
|
|
// clang-format on
|
|
}
|