Alex Bradbury fca95cfee9 [SelectionDAG] Support result type promotion for FLT_ROUNDS_ ...

For targets where i32 is not a legal type (e.g. 64-bit RISC-V), 
LegalizeIntegerTypes must promote the result of ISD::FLT_ROUNDS_.

Differential Revision: https://reviews.llvm.org/D53820

llvm-svn: 347986

2018-11-30 13:18:33 +00:00

..

CMakeLists.txt

Remove trailing whitespace to trigger re-cmaking

2017-10-02 21:54:38 +00:00

DAGCombiner.cpp

[DAGCombiner] narrow truncated binops

2018-11-29 20:58:26 +00:00

FastISel.cpp

Add support for llvm.is.constant intrinsic (PR4898)

2018-11-07 15:24:12 +00:00

FunctionLoweringInfo.cpp

DAG: Add calling convention argument to calling convention funcs

2018-07-28 13:25:19 +00:00

InstrEmitter.cpp

[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.

2018-10-26 19:32:24 +00:00

InstrEmitter.h

[DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr.

2018-05-09 02:41:08 +00:00

LegalizeDAG.cpp

[FPEnv] Add constrained CEIL/FLOOR/ROUND/TRUNC intrinsics

2018-11-05 15:59:49 +00:00

LegalizeFloatTypes.cpp

[NFC] Rename minnan and maxnan to minimum and maximum

2018-10-24 22:49:55 +00:00

LegalizeIntegerTypes.cpp

[SelectionDAG] Support result type promotion for FLT_ROUNDS_

2018-11-30 13:18:33 +00:00

LegalizeTypes.cpp

[DAG] Don't map a TableId to itself in the ReplacedValues map

2018-06-20 16:06:09 +00:00

LegalizeTypes.h

[SelectionDAG] Support result type promotion for FLT_ROUNDS_

2018-11-30 13:18:33 +00:00

LegalizeTypesGeneric.cpp

[LegalizeTypes] Fix bad indentation. NFC

2018-09-23 21:17:55 +00:00

LegalizeVectorOps.cpp

[SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps

2018-11-29 19:36:17 +00:00

LegalizeVectorTypes.cpp

[LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT.

2018-11-26 21:12:39 +00:00

LLVMBuild.txt

…

ResourcePriorityQueue.cpp

Silence a bunch of implicit fallthrough warnings

2017-12-19 22:05:25 +00:00

ScheduleDAGFast.cpp

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

ScheduleDAGRRList.cpp

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

ScheduleDAGSDNodes.cpp

llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

2018-09-27 02:13:45 +00:00

ScheduleDAGSDNodes.h

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

ScheduleDAGVLIW.cpp

ScheduleDAG: Cleanup dumping code; NFC

2018-09-19 00:23:35 +00:00

SDNodeDbgValue.h

SelectionDAG: Add compact SDDbgValue representation to -dag-dump-verbose output

2018-09-14 17:08:02 +00:00

SelectionDAG.cpp

[SelectionDAG] move constant or splat functions to common location

2018-11-25 16:09:32 +00:00

SelectionDAGAddressAnalysis.cpp

[SelectionDAG] Teach BaseIndexOffset::match to unwrap the base after looking through an add/or

2018-11-26 20:16:33 +00:00

SelectionDAGBuilder.cpp

[SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks

2018-11-20 04:30:26 +00:00

SelectionDAGBuilder.h

[IR] Add a dedicated FNeg IR Instruction

2018-11-13 18:15:47 +00:00

SelectionDAGDumper.cpp

[FPEnv] Add constrained CEIL/FLOOR/ROUND/TRUNC intrinsics

2018-11-05 15:59:49 +00:00

SelectionDAGISel.cpp

[SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks

2018-11-20 04:30:26 +00:00

SelectionDAGPrinter.cpp

Rename DEBUG macro to LLVM_DEBUG.

2018-05-14 12:53:11 +00:00

SelectionDAGTargetInfo.cpp

…

StatepointLowering.cpp

Remove trailing space

2018-07-30 19:41:25 +00:00

StatepointLowering.h

[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.

2018-03-29 17:21:10 +00:00

TargetLowering.cpp

[TargetLowering] SimplifyDemandedBits - only reduce known bits for integer constants

2018-11-21 14:26:19 +00:00