Petr Penzin 41c86ca714

[RISCV] Add TT-Ascalon-d8 processor (#115100) ...

Ascalon is an out-of-order CPU core from Tenstorrent. Overview:
https://tenstorrent.com/ip/tt-ascalon

Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be
added in a separate PR.

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Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>

2024-11-19 14:20:55 -08:00

..

aarch64.c

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amdgcn.c

AMDGPU: Add gfx950 subtarget definitions (#116307)

2024-11-18 10:41:14 -08:00

arm.c

[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU (#110085)

2024-10-14 15:48:12 +01:00

avr.c

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bpf.c

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hexagon.c

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lanai.c

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mips.c

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nvptx.c

AMDGPU: Add gfx950 subtarget definitions (#116307)

2024-11-18 10:41:14 -08:00

powerpc.c

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r600.c

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riscv.c

[RISCV] Add TT-Ascalon-d8 processor (#115100)

2024-11-19 14:20:55 -08:00

sparc.c

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systemz.c

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wasm.c

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x86.c

Reland "[X86] Support -march=diamondrapids (#113881)" (#116564)

2024-11-18 10:40:32 +08:00