Craig Topper 3e0e1c13ce

[RISCV][GISel] Support fp128 arithmetic and conversion for RV64. (#118707) ...

We can support these via libcalls in libgcc/compiler-rt or integer
operations for fneg/fabs/fcopysign. fp128 values will be passed in two
64-bit GPRs according to the psABI.

Supporting RV32 requires sret which is not supported by libcall handling
in LegalizerHelper.cpp yet. It doesn't call canLowerReturn.

2024-12-04 21:43:29 -08:00

..

instruction-select

[RISCV][GISel] Move G_BRJT expansion to legalization (#73711)

2024-11-20 13:43:36 -08:00

irtranslator

[RISCV][GISel] Allow fp128 function arguments.

2024-12-02 15:38:46 -08:00

legalizer

[RISCV][GISel] Make s16->s32 G_ANYEXT/SEXT/ZEXT legal.

2024-11-21 22:45:25 -08:00

regbankselect

[RISCV][GISel] Remove -disable-gisel-legality-check from most RVV tests. NFC

2024-11-15 12:04:55 -08:00

rvv

[RISCV][GISEL] instruction-select vmclr (#110782)

2024-10-04 12:51:04 -04:00

alu-roundtrip-rv64.ll

[GISel] Convert zext nneg to sext if it is cheaper (#93856)

2024-06-01 15:02:43 +08:00

alu-roundtrip.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

atomic-fence.ll

Reapply "[RISCV] Remove experimental from Ztso. (#96465)"

2024-07-09 10:45:56 -07:00

atomic-load-store.ll

[RISCV][GISel] Add atomic load/store test. Add additional atomic load/store isel patterns."

2024-11-20 22:23:18 -08:00

bitmanip.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calllowering-ret.ll

…

combine.ll

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

combine.mir

[GISel] Convert zext nneg to sext if it is cheaper (#93856)

2024-06-01 15:02:43 +08:00

constantpool.ll

[RISCV][GISel] Lower G_FCONSTANT to constant pool load without F or D. (#73034)

2023-12-01 10:24:26 -08:00

constbarrier-rv32.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

constbarrier-rv64.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-arith.ll

[RISCV][GISel] Copy fneg test cases from SelectionDAG into float/double-arith.ll. NFC

2024-11-26 18:20:56 -08:00

double-convert.ll

[RISCV][GISel] Stop over promoting G_SITOFP/UITOFP libcalls on RV64. (#118597)

2024-12-04 10:42:49 -08:00

double-fcmp.ll

[RISCV][GISel] Use libcalls for f32/f64 G_FCMP without F/D extensions. (#117660)

2024-11-26 15:48:49 -08:00

double-intrinsics.ll

[RISCV][GISel] Support f32/f64 ldexp. (#117941)

2024-12-02 13:30:46 -08:00

float-arith.ll

[RISCV][GISel] Copy fneg test cases from SelectionDAG into float/double-arith.ll. NFC

2024-11-26 18:20:56 -08:00

float-convert.ll

[RISCV][GISel] Stop over promoting G_SITOFP/UITOFP libcalls on RV64. (#118597)

2024-12-04 10:42:49 -08:00

float-fclass.ll

[RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection (#118021)

2024-12-02 11:19:08 -08:00

float-fcmp.ll

[RISCV][GISel] Use libcalls for f32/f64 G_FCMP without F/D extensions. (#117660)

2024-11-26 15:48:49 -08:00

float-intrinsics.ll

[RISCV][GISel] Support f32/f64 ldexp. (#117941)

2024-12-02 13:30:46 -08:00

fp128.ll

[RISCV][GISel] Support fp128 arithmetic and conversion for RV64. (#118707)

2024-12-04 21:43:29 -08:00

fpr-gpr-copy-rv32.ll

[RISCV] Teach copyPhysReg to allow copies between GPR<->FPR32/FPR64 (#70525)

2023-10-30 09:58:51 -07:00

fpr-gpr-copy-rv64.ll

[RISCV][GISel] Add missing curly brace to test. NFC

2023-10-30 10:12:56 -07:00

freeze.ll

[RISCV][GISel] Make loads/stores with s16 register type and s16 memory type legal.

2024-11-17 11:39:59 -08:00

gisel-commandline-option.ll

Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"

2024-09-20 07:01:17 -07:00

iabs.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

irtranslator-calllowering.ll

…

jumptable.ll

[RISCV][GISel] Move G_BRJT expansion to legalization (#73711)

2024-11-20 13:43:36 -08:00

legalizer-info-validation.mir

[RISCV][GISel] Stop over promoting G_SITOFP/UITOFP libcalls on RV64. (#118597)

2024-12-04 10:42:49 -08:00

libcalls.ll

[GISel][RISCV] Legalize G_FREM (#93063)

2024-05-24 00:34:06 +08:00

rv32zba.ll

[RISCV][GISel] Copy some Zba IR test cases from SelectionDAG. NFC

2024-11-14 13:47:49 -08:00

rv32zbb-zbkb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv32zbb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv32zbkb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64-double-convert.ll

[RISCV][GISel] Improve fptos/ui and s/uitofp handling and testing.

2024-11-06 12:18:56 -08:00

rv64-float-convert.ll

[RISCV][GISel] Improve fptos/ui and s/uitofp handling and testing.

2024-11-06 12:18:56 -08:00

rv64zba.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64zbb-zbkb.ll

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

rv64zbb.ll

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

rv64zbkb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

scalablevec-combiner-crash.ll

[GlobalISel] Add bail outs for scalable vectors to some combines. (#106496)

2024-08-29 14:02:53 -07:00

shift.ll

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)

2024-11-11 20:59:21 -08:00

stacksave-stackrestore.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

vararg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00