hev 99d63c64f8

[LoongArch] Fix assertion when combining SETCC with wide constants (#172975) ...

Fixes #172964

2025-12-20 00:21:17 +08:00

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AArch64

[AArch64] Fix assertion failure during promotion of EXTEND_VECTOR_INREG. (#171619)

2025-12-19 17:05:35 +01:00

AMDGPU

AMDGPU: Add baseline tests for f64 rsq pattern handling (#172052)

2025-12-19 10:12:25 +01:00

ARC

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ARM

[CodeGen] Rename expand-fp to expand-ir-insts (#172681)

2025-12-18 11:15:04 +00:00

AVR

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BPF

Revert "[BPF] Allow libcalls behind a feature gate (#168442)" (#169733)

2025-12-01 11:19:39 -08:00

CSKY

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DirectX

[DirectX] Move memset and memcpy handling to a new pass. NFC (#172921)

2025-12-18 22:08:43 -07:00

Generic

fix llvm.fma.f16 double rounding issue when there is no native support (#171904)

2025-12-17 22:03:01 +01:00

Hexagon

[Hexagon] Add HVX patterns for vector arithmetic (#170704)

2025-12-11 16:44:01 -06:00

Inputs

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Lanai

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LoongArch

[LoongArch] Fix assertion when combining SETCC with wide constants (#172975)

2025-12-20 00:21:17 +08:00

M68k

[CodeGen] Rename expand-fp to expand-ir-insts (#172681)

2025-12-18 11:15:04 +00:00

Mips

[mips][micromips] Add mayRaiseFPException to appropriate instructions, mark all instructions that read FCSR (FCR31) rounding bits as doing so (#170322)

2025-12-18 23:06:36 +01:00

MIR

[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction (#151944)

2025-12-03 13:56:15 +05:30

MIR2Vec

[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction (#151944)

2025-12-03 13:56:15 +05:30

MLRegAlloc

[MLGO] Remove Extra Dev Mode Features (#167273)

2025-11-10 08:40:28 -08:00

MSP430

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NVPTX

[NVPTX] Add missing type suffixes for barrier.cta.red (#172945)

2025-12-19 05:53:49 -08:00

PowerPC

[CodeGen] Rename expand-fp to expand-ir-insts (#172681)

2025-12-18 11:15:04 +00:00

RISCV

[RISCV][llvm] Remove custom legalization of fixed-length vector SPLAT_VECTOR (#172870)

2025-12-19 11:45:10 +08:00

SPARC

[SPARC][NFC] Update optcompare test that always returns false (#170025)

2025-12-05 20:35:03 +07:00

SPIRV

[SPIRV] Restrict OpName generation to major values (#171886)

2025-12-18 19:46:59 +00:00

SystemZ

[RegisterCoalescer] Don't commute two-address instructions which only define a subregister (#169031)

2025-12-18 23:24:44 +01:00

Thumb

[DAG] Fold mul 0 -> 0 when expanding mul into parts. (#168780)

2025-12-05 07:58:28 +00:00

Thumb2

[ARM] Introduce intrinsics for MVE fp-converts under strict-fp. (#170686)

2025-12-14 12:12:45 +00:00

VE

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WebAssembly

Revert "[WebAssembly] Implement addrspacecast to funcref" (#170785)

2025-12-04 17:24:14 -08:00

WinCFGuard

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WinEH

[IR] Update PHINode::removeIncomingValueIf() to use the swap strategy like PHINode::removeIncomingValue() (#172639)

2025-12-18 09:09:50 +08:00

X86

[X86] combineConcatVectorOps - add handling for FNEG vector ops (#172996)

2025-12-19 13:00:08 +00:00

XCore

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Xtensa

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