Matt Arsenault 3c5e4237c6 AMDGPU: Make some packed shuffles free ...

VOP3P instructions can encode access to either
half of the register.

llvm-svn: 302730

2017-05-10 21:29:33 +00:00

..

AArch64

[AArch64] Consider widening instructions in cost calculations

2017-05-09 20:18:12 +00:00

AMDGPU

AMDGPU: Make some packed shuffles free

2017-05-10 21:29:33 +00:00

ARM

[TTI/CostModel] Correct the way getGEPCost() calls isLegalAddressingMode()

2016-12-03 01:57:24 +00:00

PowerPC

[PPC] Give unaligned memory access lower cost on processor that supports it

2017-02-17 22:29:39 +00:00

SystemZ

[SystemZ] Fix target specific tests

2017-04-12 17:14:46 +00:00

X86

[X86][AVX1] Improve 256-bit vector costs for integer unary intrinsics.

2017-05-07 20:58:55 +00:00

no_info.ll

Roll forward r243250

2015-07-26 19:10:03 +00:00