2484060ad9
Any kill flags that were present for the old register are not valid for the replacement and the replacement may have extended the live range of the replacement register.
284 lines
9.0 KiB
C++
284 lines
9.0 KiB
C++
//===- RISCVFoldMemOffset.cpp - Fold ADDI into memory offsets ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===---------------------------------------------------------------------===//
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//
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// Look for ADDIs that can be removed by folding their immediate into later
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// load/store addresses. There may be other arithmetic instructions between the
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// addi and load/store that we need to reassociate through. If the final result
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// of the arithmetic is only used by load/store addresses, we can fold the
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// offset into the all the load/store as long as it doesn't create an offset
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// that is too large.
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//
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//===---------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include <queue>
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using namespace llvm;
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#define DEBUG_TYPE "riscv-fold-mem-offset"
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#define RISCV_FOLD_MEM_OFFSET_NAME "RISC-V Fold Memory Offset"
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namespace {
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class RISCVFoldMemOffset : public MachineFunctionPass {
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public:
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static char ID;
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RISCVFoldMemOffset() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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bool foldOffset(Register OrigReg, int64_t InitialOffset,
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const MachineRegisterInfo &MRI,
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DenseMap<MachineInstr *, int64_t> &FoldableInstrs);
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return RISCV_FOLD_MEM_OFFSET_NAME; }
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};
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// Wrapper class around a std::optional to allow accumulation.
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class FoldableOffset {
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std::optional<int64_t> Offset;
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public:
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bool hasValue() const { return Offset.has_value(); }
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int64_t getValue() const { return *Offset; }
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FoldableOffset &operator=(int64_t RHS) {
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Offset = RHS;
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return *this;
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}
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FoldableOffset &operator+=(int64_t RHS) {
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if (!Offset)
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Offset = 0;
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Offset = (uint64_t)*Offset + (uint64_t)RHS;
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return *this;
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}
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int64_t operator*() { return *Offset; }
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};
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} // end anonymous namespace
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char RISCVFoldMemOffset::ID = 0;
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INITIALIZE_PASS(RISCVFoldMemOffset, DEBUG_TYPE, RISCV_FOLD_MEM_OFFSET_NAME,
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false, false)
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FunctionPass *llvm::createRISCVFoldMemOffsetPass() {
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return new RISCVFoldMemOffset();
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}
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// Walk forward from the ADDI looking for arithmetic instructions we can
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// analyze or memory instructions that use it as part of their address
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// calculation. For each arithmetic instruction we lookup how the offset
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// contributes to the value in that register use that information to
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// calculate the contribution to the output of this instruction.
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// Only addition and left shift are supported.
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// FIXME: Add multiplication by constant. The constant will be in a register.
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bool RISCVFoldMemOffset::foldOffset(
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Register OrigReg, int64_t InitialOffset, const MachineRegisterInfo &MRI,
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DenseMap<MachineInstr *, int64_t> &FoldableInstrs) {
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// Map to hold how much the offset contributes to the value of this register.
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DenseMap<Register, int64_t> RegToOffsetMap;
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// Insert root offset into the map.
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RegToOffsetMap[OrigReg] = InitialOffset;
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std::queue<Register> Worklist;
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Worklist.push(OrigReg);
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while (!Worklist.empty()) {
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Register Reg = Worklist.front();
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Worklist.pop();
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if (!Reg.isVirtual())
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return false;
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for (auto &User : MRI.use_nodbg_instructions(Reg)) {
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FoldableOffset Offset;
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switch (User.getOpcode()) {
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default:
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return false;
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case RISCV::ADD:
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if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg());
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I != RegToOffsetMap.end())
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Offset = I->second;
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if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg());
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I != RegToOffsetMap.end())
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Offset += I->second;
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break;
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case RISCV::SH1ADD:
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if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg());
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I != RegToOffsetMap.end())
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Offset = (uint64_t)I->second << 1;
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if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg());
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I != RegToOffsetMap.end())
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Offset += I->second;
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break;
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case RISCV::SH2ADD:
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if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg());
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I != RegToOffsetMap.end())
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Offset = (uint64_t)I->second << 2;
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if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg());
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I != RegToOffsetMap.end())
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Offset += I->second;
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break;
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case RISCV::SH3ADD:
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if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg());
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I != RegToOffsetMap.end())
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Offset = (uint64_t)I->second << 3;
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if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg());
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I != RegToOffsetMap.end())
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Offset += I->second;
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break;
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case RISCV::ADD_UW:
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case RISCV::SH1ADD_UW:
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case RISCV::SH2ADD_UW:
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case RISCV::SH3ADD_UW:
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// Don't fold through the zero extended input.
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if (User.getOperand(1).getReg() == Reg)
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return false;
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if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg());
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I != RegToOffsetMap.end())
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Offset = I->second;
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break;
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case RISCV::SLLI: {
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unsigned ShAmt = User.getOperand(2).getImm();
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if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg());
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I != RegToOffsetMap.end())
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Offset = (uint64_t)I->second << ShAmt;
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break;
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}
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case RISCV::LB:
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case RISCV::LBU:
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case RISCV::SB:
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case RISCV::LH:
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case RISCV::LH_INX:
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case RISCV::LHU:
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case RISCV::FLH:
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case RISCV::SH:
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case RISCV::SH_INX:
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case RISCV::FSH:
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case RISCV::LW:
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case RISCV::LW_INX:
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case RISCV::LWU:
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case RISCV::FLW:
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case RISCV::SW:
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case RISCV::SW_INX:
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case RISCV::FSW:
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case RISCV::LD:
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case RISCV::FLD:
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case RISCV::SD:
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case RISCV::FSD: {
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// Can't fold into store value.
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if (User.getOperand(0).getReg() == Reg)
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return false;
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// Existing offset must be immediate.
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if (!User.getOperand(2).isImm())
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return false;
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// Require at least one operation between the ADDI and the load/store.
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// We have other optimizations that should handle the simple case.
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if (User.getOperand(1).getReg() == OrigReg)
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return false;
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auto I = RegToOffsetMap.find(User.getOperand(1).getReg());
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if (I == RegToOffsetMap.end())
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return false;
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int64_t LocalOffset = User.getOperand(2).getImm();
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assert(isInt<12>(LocalOffset));
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int64_t CombinedOffset = (uint64_t)LocalOffset + (uint64_t)I->second;
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if (!isInt<12>(CombinedOffset))
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return false;
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FoldableInstrs[&User] = CombinedOffset;
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continue;
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}
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}
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// If we reach here we should have an accumulated offset.
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assert(Offset.hasValue() && "Expected an offset");
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// If the offset is new or changed, add the destination register to the
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// work list.
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int64_t OffsetVal = Offset.getValue();
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auto P =
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RegToOffsetMap.try_emplace(User.getOperand(0).getReg(), OffsetVal);
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if (P.second) {
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Worklist.push(User.getOperand(0).getReg());
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} else if (P.first->second != OffsetVal) {
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P.first->second = OffsetVal;
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Worklist.push(User.getOperand(0).getReg());
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}
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}
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}
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return true;
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}
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bool RISCVFoldMemOffset::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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// This optimization may increase size by preventing compression.
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if (MF.getFunction().hasOptSize())
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return false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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bool MadeChange = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
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// FIXME: We can support ADDIW from an LUI+ADDIW pair if the result is
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// equivalent to LUI+ADDI.
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if (MI.getOpcode() != RISCV::ADDI)
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continue;
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// We only want to optimize register ADDIs.
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if (!MI.getOperand(1).isReg() || !MI.getOperand(2).isImm())
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continue;
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// Ignore 'li'.
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if (MI.getOperand(1).getReg() == RISCV::X0)
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continue;
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int64_t Offset = MI.getOperand(2).getImm();
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assert(isInt<12>(Offset));
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DenseMap<MachineInstr *, int64_t> FoldableInstrs;
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if (!foldOffset(MI.getOperand(0).getReg(), Offset, MRI, FoldableInstrs))
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continue;
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if (FoldableInstrs.empty())
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continue;
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// We can fold this ADDI.
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// Rewrite all the instructions.
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for (auto [MemMI, NewOffset] : FoldableInstrs)
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MemMI->getOperand(2).setImm(NewOffset);
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MRI.replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
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MRI.clearKillFlags(MI.getOperand(1).getReg());
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MI.eraseFromParent();
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}
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}
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return MadeChange;
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}
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