fe4f6c1a58
When vectorizing with predication some loops that were previously vectorized without zvfhmin/zvfbfmin will no longer be vectorized because the masked load/store or gather/scatter cost returns illegal. This is due to a discrepancy where for these costs we check isLegalElementTypeForRVV but for regular memory accesses we don't. But for bf16 and f16 vectors we don't actually need the extension support for loads and stores, so this adds a new function which takes this into account. For regular memory accesses we should probably also e.g. return an invalid cost for i64 elements on zve32x, but it doesn't look like we have tests for this yet. We also should probably not be vectorizing these bf16/f16 loops to begin with if we don't have zvfhmin/zvfbfmin and zfhmin/zfbfmin. I think this is due to the scalar costs being too cheap. I've added tests for this in a100f6367205c6a909d68027af6a8675a8091bd9 to fix in another patch.
480 lines
20 KiB
C++
480 lines
20 KiB
C++
//===- RISCVTargetTransformInfo.h - RISC-V specific TTI ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines a TargetTransformInfoImplBase conforming object specific
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/// to the RISC-V target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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#include <optional>
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namespace llvm {
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class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
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using BaseT = BasicTTIImplBase<RISCVTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const RISCVSubtarget *ST;
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const RISCVTargetLowering *TLI;
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const RISCVSubtarget *getST() const { return ST; }
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const RISCVTargetLowering *getTLI() const { return TLI; }
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/// This function returns an estimate for VL to be used in VL based terms
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/// of the cost model. For fixed length vectors, this is simply the
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/// vector length. For scalable vectors, we return results consistent
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/// with getVScaleForTuning under the assumption that clients are also
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/// using that when comparing costs between scalar and vector representation.
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/// This does unfortunately mean that we can both undershoot and overshot
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/// the true cost significantly if getVScaleForTuning is wildly off for the
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/// actual target hardware.
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unsigned getEstimatedVLFor(VectorType *Ty) const;
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/// This function calculates the costs for one or more RVV opcodes based
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/// on the vtype and the cost kind.
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/// \param Opcodes A list of opcodes of the RVV instruction to evaluate.
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/// \param VT The MVT of vtype associated with the RVV instructions.
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/// For widening/narrowing instructions where the result and source types
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/// differ, it is important to check the spec to determine whether the vtype
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/// refers to the result or source type.
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/// \param CostKind The type of cost to compute.
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InstructionCost getRISCVInstructionCost(ArrayRef<unsigned> OpCodes, MVT VT,
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TTI::TargetCostKind CostKind) const;
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/// Return the cost of accessing a constant pool entry of the specified
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/// type.
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InstructionCost getConstantPoolLoadCost(Type *Ty,
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TTI::TargetCostKind CostKind) const;
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/// If this shuffle can be lowered as a masked slide pair (at worst),
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/// return a cost for it.
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InstructionCost getSlideCost(FixedVectorType *Tp, ArrayRef<int> Mask,
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TTI::TargetCostKind CostKind) const;
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public:
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explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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/// Return the cost of materializing an immediate for a value operand of
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/// a store instruction.
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InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo,
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TTI::TargetCostKind CostKind) const;
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InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind,
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Instruction *Inst = nullptr) const override;
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InstructionCost
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getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind) const override;
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/// \name EVL Support for predicated vectorization.
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/// Whether the target supports the %evl parameter of VP intrinsic efficiently
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/// in hardware. (see LLVM Language Reference - "Vector Predication
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/// Intrinsics",
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/// https://llvm.org/docs/LangRef.html#vector-predication-intrinsics and
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/// "IR-level VP intrinsics",
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/// https://llvm.org/docs/Proposals/VectorPredication.html#ir-level-vp-intrinsics).
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bool hasActiveVectorLength() const override;
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TargetTransformInfo::PopcntSupportKind
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getPopcntSupport(unsigned TyWidth) const override;
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InstructionCost getPartialReductionCost(
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unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
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ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
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TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
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TTI::TargetCostKind CostKind) const override;
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bool shouldExpandReduction(const IntrinsicInst *II) const override;
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bool supportsScalableVectors() const override {
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return ST->hasVInstructions();
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}
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bool enableOrderedReductions() const override { return true; }
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bool enableScalableVectorization() const override {
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return ST->hasVInstructions();
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}
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TailFoldingStyle
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getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const override {
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return ST->hasVInstructions() ? TailFoldingStyle::DataWithEVL
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: TailFoldingStyle::None;
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}
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std::optional<unsigned> getMaxVScale() const override;
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std::optional<unsigned> getVScaleForTuning() const override;
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TypeSize
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getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override;
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unsigned getRegUsageForType(Type *Ty) const override;
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unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override;
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bool preferAlternateOpcodeVectorization() const override { return false; }
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bool preferEpilogueVectorization() const override {
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// Epilogue vectorization is usually unprofitable - tail folding or
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// a smaller VF would have been better. This a blunt hammer - we
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// should re-examine this once vectorization is better tuned.
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return false;
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}
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InstructionCost
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getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost
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getPointersChainCost(ArrayRef<const Value *> Ptrs, const Value *Base,
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const TTI::PointersChainInfo &Info, Type *AccessTy,
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TTI::TargetCostKind CostKind) const override;
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE) const override;
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP) const override;
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unsigned getMinVectorRegisterBitWidth() const override {
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return ST->useRVVForFixedLengthVectors() ? 16 : 0;
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}
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InstructionCost
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getShuffleCost(TTI::ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
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ArrayRef<int> Mask, TTI::TargetCostKind CostKind, int Index,
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VectorType *SubTp, ArrayRef<const Value *> Args = {},
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const Instruction *CxtI = nullptr) const override;
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InstructionCost getScalarizationOverhead(
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VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
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TTI::TargetCostKind CostKind, bool ForPoisonSrc = true,
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ArrayRef<Value *> VL = {}) const override;
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InstructionCost
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getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
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bool UseMaskForCond = false, bool UseMaskForGaps = false) const override;
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InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
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const Value *Ptr, bool VariableMask,
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Align Alignment,
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TTI::TargetCostKind CostKind,
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const Instruction *I) const override;
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InstructionCost
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getExpandCompressMemoryOpCost(unsigned Opcode, Type *Src, bool VariableMask,
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Align Alignment, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr) const override;
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InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy,
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const Value *Ptr, bool VariableMask,
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Align Alignment,
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TTI::TargetCostKind CostKind,
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const Instruction *I) const override;
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InstructionCost
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getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const override;
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InstructionCost
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getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::CastContextHint CCH, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr) const override;
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InstructionCost
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getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost
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getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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std::optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost
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getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy,
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VectorType *ValTy, std::optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost getMemoryOpCost(
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unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo OpdInfo = {TTI::OK_AnyValue, TTI::OP_None},
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const Instruction *I = nullptr) const override;
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InstructionCost getCmpSelInstrCost(
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unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
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TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
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TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
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const Instruction *I = nullptr) const override;
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InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr) const override;
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using BaseT::getVectorInstrCost;
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InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
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TTI::TargetCostKind CostKind,
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unsigned Index, const Value *Op0,
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const Value *Op1) const override;
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InstructionCost getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
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TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
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ArrayRef<const Value *> Args = {},
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const Instruction *CxtI = nullptr) const override;
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bool isElementTypeLegalForScalableVector(Type *Ty) const override {
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return TLI->isLegalElementTypeForRVV(TLI->getValueType(DL, Ty));
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}
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bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) const {
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if (!ST->hasVInstructions())
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return false;
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EVT DataTypeVT = TLI->getValueType(DL, DataType);
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// Only support fixed vectors if we know the minimum vector size.
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if (DataTypeVT.isFixedLengthVector() && !ST->useRVVForFixedLengthVectors())
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return false;
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EVT ElemType = DataTypeVT.getScalarType();
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if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
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return false;
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return TLI->isLegalLoadStoreElementTypeForRVV(ElemType);
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}
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bool isLegalMaskedLoad(Type *DataType, Align Alignment,
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unsigned /*AddressSpace*/) const override {
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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bool isLegalMaskedStore(Type *DataType, Align Alignment,
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unsigned /*AddressSpace*/) const override {
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment) const {
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if (!ST->hasVInstructions())
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return false;
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EVT DataTypeVT = TLI->getValueType(DL, DataType);
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// Only support fixed vectors if we know the minimum vector size.
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if (DataTypeVT.isFixedLengthVector() && !ST->useRVVForFixedLengthVectors())
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return false;
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// We also need to check if the vector of address is valid.
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EVT PointerTypeVT = EVT(TLI->getPointerTy(DL));
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if (DataTypeVT.isScalableVector() &&
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!TLI->isLegalElementTypeForRVV(PointerTypeVT))
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return false;
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EVT ElemType = DataTypeVT.getScalarType();
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if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
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return false;
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return TLI->isLegalLoadStoreElementTypeForRVV(ElemType);
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}
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bool isLegalMaskedGather(Type *DataType, Align Alignment) const override {
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return isLegalMaskedGatherScatter(DataType, Alignment);
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}
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bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override {
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return isLegalMaskedGatherScatter(DataType, Alignment);
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}
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bool forceScalarizeMaskedGather(VectorType *VTy,
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Align Alignment) const override {
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// Scalarize masked gather for RV64 if EEW=64 indices aren't supported.
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return ST->is64Bit() && !ST->hasVInstructionsI64();
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}
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bool forceScalarizeMaskedScatter(VectorType *VTy,
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Align Alignment) const override {
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// Scalarize masked scatter for RV64 if EEW=64 indices aren't supported.
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return ST->is64Bit() && !ST->hasVInstructionsI64();
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}
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bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const override {
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EVT DataTypeVT = TLI->getValueType(DL, DataType);
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return TLI->isLegalStridedLoadStore(DataTypeVT, Alignment);
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}
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bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
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Align Alignment,
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unsigned AddrSpace) const override {
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return TLI->isLegalInterleavedAccessType(VTy, Factor, Alignment, AddrSpace,
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DL);
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}
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bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const override;
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bool isLegalMaskedCompressStore(Type *DataTy, Align Alignment) const override;
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bool isVScaleKnownToBeAPowerOfTwo() const override {
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return TLI->isVScaleKnownToBeAPowerOfTwo();
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}
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/// \returns How the target needs this vector-predicated operation to be
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/// transformed.
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TargetTransformInfo::VPLegalization
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getVPLegalizationStrategy(const VPIntrinsic &PI) const override {
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using VPLegalization = TargetTransformInfo::VPLegalization;
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if (!ST->hasVInstructions() ||
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(PI.getIntrinsicID() == Intrinsic::vp_reduce_mul &&
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cast<VectorType>(PI.getArgOperand(1)->getType())
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->getElementType()
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->getIntegerBitWidth() != 1))
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return VPLegalization(VPLegalization::Discard, VPLegalization::Convert);
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return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
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}
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bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc,
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ElementCount VF) const override {
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if (!VF.isScalable())
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return true;
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Type *Ty = RdxDesc.getRecurrenceType();
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if (!TLI->isLegalElementTypeForRVV(TLI->getValueType(DL, Ty)))
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return false;
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switch (RdxDesc.getRecurrenceKind()) {
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case RecurKind::Add:
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case RecurKind::And:
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case RecurKind::Or:
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case RecurKind::Xor:
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case RecurKind::SMin:
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case RecurKind::SMax:
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case RecurKind::UMin:
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case RecurKind::UMax:
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case RecurKind::FMin:
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case RecurKind::FMax:
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return true;
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case RecurKind::AnyOf:
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case RecurKind::FAdd:
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case RecurKind::FMulAdd:
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// We can't promote f16/bf16 fadd reductions and scalable vectors can't be
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// expanded.
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if (Ty->isBFloatTy() || (Ty->isHalfTy() && !ST->hasVInstructionsF16()))
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return false;
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return true;
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default:
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return false;
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}
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}
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unsigned getMaxInterleaveFactor(ElementCount VF) const override {
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// Don't interleave if the loop has been vectorized with scalable vectors.
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if (VF.isScalable())
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return 1;
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// If the loop will not be vectorized, don't interleave the loop.
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// Let regular unroll to unroll the loop.
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return VF.isScalar() ? 1 : ST->getMaxInterleaveFactor();
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}
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bool enableInterleavedAccessVectorization() const override { return true; }
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unsigned getMinTripCountTailFoldingThreshold() const override;
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enum RISCVRegisterClass { GPRRC, FPRRC, VRRC };
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unsigned getNumberOfRegisters(unsigned ClassID) const override {
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switch (ClassID) {
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case RISCVRegisterClass::GPRRC:
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// 31 = 32 GPR - x0 (zero register)
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// FIXME: Should we exclude fixed registers like SP, TP or GP?
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return 31;
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case RISCVRegisterClass::FPRRC:
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if (ST->hasStdExtF())
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return 32;
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return 0;
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case RISCVRegisterClass::VRRC:
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// Although there are 32 vector registers, v0 is special in that it is the
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// only register that can be used to hold a mask.
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// FIXME: Should we conservatively return 31 as the number of usable
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// vector registers?
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return ST->hasVInstructions() ? 32 : 0;
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}
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llvm_unreachable("unknown register class");
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}
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TTI::AddressingModeKind
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getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const override;
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unsigned getRegisterClassForType(bool Vector,
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Type *Ty = nullptr) const override {
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if (Vector)
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return RISCVRegisterClass::VRRC;
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if (!Ty)
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return RISCVRegisterClass::GPRRC;
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Type *ScalarTy = Ty->getScalarType();
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if ((ScalarTy->isHalfTy() && ST->hasStdExtZfhmin()) ||
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(ScalarTy->isFloatTy() && ST->hasStdExtF()) ||
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(ScalarTy->isDoubleTy() && ST->hasStdExtD())) {
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return RISCVRegisterClass::FPRRC;
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}
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return RISCVRegisterClass::GPRRC;
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}
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const char *getRegisterClassName(unsigned ClassID) const override {
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switch (ClassID) {
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case RISCVRegisterClass::GPRRC:
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return "RISCV::GPRRC";
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case RISCVRegisterClass::FPRRC:
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return "RISCV::FPRRC";
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case RISCVRegisterClass::VRRC:
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return "RISCV::VRRC";
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}
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llvm_unreachable("unknown register class");
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}
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bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
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const TargetTransformInfo::LSRCost &C2) const override;
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bool shouldConsiderAddressTypePromotion(
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const Instruction &I,
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bool &AllowPromotionWithoutCommonHeader) const override;
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std::optional<unsigned> getMinPageSize() const override { return 4096; }
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/// Return true if the (vector) instruction I will be lowered to an
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/// instruction with a scalar splat operand for the given Operand number.
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bool canSplatOperand(Instruction *I, int Operand) const;
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/// Return true if a vector instruction will lower to a target instruction
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/// able to splat the given operand.
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bool canSplatOperand(unsigned Opcode, int Operand) const;
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bool isProfitableToSinkOperands(Instruction *I,
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SmallVectorImpl<Use *> &Ops) const override;
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TTI::MemCmpExpansionOptions
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enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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