52a9c493e6
The defmask vector cannot contain instructions that use V0. for `MultiSource/Benchmarks/DOE-ProxyApps-C++/CLAMR/mesh.cpp` Save `%173:vrm2nov0 = PseudoVMERGE_VVM_M2 undef %173:vrm2nov0(tied-def 0), %116:vrm2, %173:vrm2nov0, killed $v0, -1, 5 `to def mask caused crash.
111 lines
3.8 KiB
C++
111 lines
3.8 KiB
C++
//===- RISCVVectorMaskDAGMutation.cpp - RISC-V Vector Mask DAGMutation ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// A schedule mutation that adds an artificial dependency between masks producer
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// instructions and masked instructions, so that we can reduce the live range
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// overlaps of mask registers.
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//
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// If there are multiple masks producers followed by multiple masked
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// instructions, then at each masked instructions add dependency edges between
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// every producer and masked instruction.
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//
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// The reason why we need to do this:
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// 1. When tracking register pressure, we don't track physical registers.
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// 2. We have a RegisterClass for mask register (which is `VMV0`), but we don't
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// use it by the time we reach scheduling. Instead, we use physical
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// register V0 directly and insert a `$v0 = COPY ...` before the use.
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// 3. For mask producers, we are using VR RegisterClass (we can allocate V0-V31
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// to it). So if V0 is not available, there are still 31 available registers
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// out there.
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//
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// This means that the RegPressureTracker can't track the pressure of mask
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// registers correctly.
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//
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// This schedule mutation is a workaround to fix this issue.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#define DEBUG_TYPE "machine-scheduler"
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namespace llvm {
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static bool isCopyToV0(const MachineInstr &MI) {
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return MI.isFullCopy() && MI.getOperand(0).getReg() == RISCV::V0 &&
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MI.getOperand(1).getReg().isVirtual();
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}
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static bool isSoleUseCopyToV0(SUnit &SU) {
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if (SU.Succs.size() != 1)
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return false;
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SDep &Dep = SU.Succs[0];
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// Ignore dependencies other than data or strong ordering.
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if (Dep.isWeak())
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return false;
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SUnit &DepSU = *Dep.getSUnit();
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if (DepSU.isBoundaryNode())
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return false;
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return isCopyToV0(*DepSU.getInstr());
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}
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class RISCVVectorMaskDAGMutation : public ScheduleDAGMutation {
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private:
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const TargetRegisterInfo *TRI;
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public:
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RISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI) : TRI(TRI) {}
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void apply(ScheduleDAGInstrs *DAG) override {
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SUnit *NearestUseV0SU = nullptr;
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SmallVector<SUnit *, 2> DefMask;
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for (SUnit &SU : DAG->SUnits) {
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const MachineInstr *MI = SU.getInstr();
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bool UseV0 = MI->findRegisterUseOperand(RISCV::V0, TRI);
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if (isSoleUseCopyToV0(SU) && !UseV0)
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DefMask.push_back(&SU);
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if (UseV0) {
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NearestUseV0SU = &SU;
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// Copy may not be a real use, so skip it here.
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if (DefMask.size() > 1 && !MI->isCopy()) {
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for (SUnit *Def : DefMask)
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if (DAG->canAddEdge(Def, &SU))
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DAG->addEdge(Def, SDep(&SU, SDep::Artificial));
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}
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if (!DefMask.empty())
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DefMask.erase(DefMask.begin());
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}
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if (NearestUseV0SU && NearestUseV0SU != &SU && isSoleUseCopyToV0(SU) &&
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// For LMUL=8 cases, there will be more possibilities to spill.
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// FIXME: We should use RegPressureTracker to do fine-grained
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// controls.
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RISCVII::getLMul(MI->getDesc().TSFlags) != RISCVVType::LMUL_8)
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DAG->addEdge(&SU, SDep(NearestUseV0SU, SDep::Artificial));
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}
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}
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};
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std::unique_ptr<ScheduleDAGMutation>
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createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI) {
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return std::make_unique<RISCVVectorMaskDAGMutation>(TRI);
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}
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} // namespace llvm
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