fe544d404d
When https://github.com/llvm/llvm-project/pull/130034 enabled RISC-V here I noticed that these should run for ARM as well. ARM only has 4 argument registers, which matches Arm's ABI for it: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#core-registers The ABI defines a link register LR, and I assume that's what becomes 'ra' in LLDB. Tested on ARM and AArch64 Linux.