Matt Arsenault fe78ffba92 AMDGPU: Fix folding reg_sequence into copy to phys reg ...

This was producing an illegal reg_sequence defining
a physical register with virtual register inputs.

llvm-svn: 299997

2017-04-11 22:29:19 +00:00

..

AArch64

[GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 types

2017-04-11 10:10:14 +00:00

AMDGPU

AMDGPU: Fix folding reg_sequence into copy to phys reg

2017-04-11 22:29:19 +00:00

ARM

GlobalISel: Allow legalizing G_FADD to a libcall

2017-04-11 10:52:34 +00:00

AVR

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BPF

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

Generic

[ARM] Try to re-enable MachineBranchProb.ll for ARM/AArch64

2017-04-05 16:27:11 +00:00

Hexagon

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

Inputs

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Lanai

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Mips

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

MIR

MIR: Allow parsing of empty machine functions

2017-04-11 19:32:41 +00:00

MSP430

In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.

2017-03-14 00:34:14 +00:00

NVPTX

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

PowerPC

[PowerPC] multiply-with-overflow might use the CTR register

2017-04-11 02:03:17 +00:00

SPARC

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SystemZ

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

Thumb

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

Thumb2

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

WebAssembly

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WinEH

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X86

[DAGCombine] Add more test cases for shuffle of splat. NFC.

2017-04-11 21:16:59 +00:00

XCore

In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.

2017-03-14 00:34:14 +00:00