875b10f7d0
We have defined `__riscv_cpu_model` variable in #101449. It contains `mvendorid`, `marchid` and `mimpid` fields which are read via system call `sys_riscv_hwprobe`. We can support `__builtin_cpu_is` via comparing values in compiler's CPU definitions and `__riscv_cpu_model`. This depends on #116202. Reviewers: lenary, BeMg, kito-cheng, preames, lukel97 Reviewed By: lenary Pull Request: https://github.com/llvm/llvm-project/pull/116231
40 lines
2.3 KiB
C
40 lines
2.3 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm %s -o - \
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// RUN: | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
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// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(
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// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: [[ENTRY:.*:]]
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
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// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
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// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
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// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
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// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
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// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
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// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
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// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
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// CHECK-RV64-NEXT: ret i32 [[CONV]]
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//
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int test_cpu_is_veyron_v1() {
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return __builtin_cpu_is("veyron-v1");
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}
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// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_spacemit_x60(
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// CHECK-RV64-SAME: ) #[[ATTR0]] {
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// CHECK-RV64-NEXT: [[ENTRY:.*:]]
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1808
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// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
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// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372035378380799
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// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
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// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
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// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1152921505839391232
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// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
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// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
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// CHECK-RV64-NEXT: ret i32 [[CONV]]
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//
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int test_cpu_is_spacemit_x60() {
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return __builtin_cpu_is("spacemit-x60");
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}
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