158d72d728
Set the writable and dead_on_unwind attributes for sret arguments. These indicate that the argument points to writable memory (and it's legal to introduce spurious writes to it on entry to the function) and that the argument memory will not be used if the call unwinds. This enables additional MemCpyOpt/DSE/LICM optimizations.
136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
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// RUN: | FileCheck %s
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// Basic argument tests for ARC.
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// CHECK: define{{.*}} void @f0(i32 inreg noundef %i, i32 inreg noundef %j, i64 inreg noundef %k)
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void f0(int i, long j, long long k) {}
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typedef struct {
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int aa;
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int bb;
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} s1;
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// CHECK: define{{.*}} void @f1(i32 inreg %i.coerce0, i32 inreg %i.coerce1)
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void f1(s1 i) {}
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typedef struct {
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char aa; char bb; char cc; char dd;
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} cs1;
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// CHECK: define{{.*}} void @cf1(i32 inreg %i.coerce)
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void cf1(cs1 i) {}
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typedef struct {
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int cc;
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} s2;
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// CHECK: define{{.*}} void @f2(ptr dead_on_unwind noalias writable sret(%struct.s2) align 4 %agg.result)
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s2 f2(void) {
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s2 foo;
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return foo;
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}
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typedef struct {
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int cc;
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int dd;
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} s3;
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// CHECK: define{{.*}} void @f3(ptr dead_on_unwind noalias writable sret(%struct.s3) align 4 %agg.result)
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s3 f3(void) {
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s3 foo;
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return foo;
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}
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// CHECK: define{{.*}} void @f4(i64 inreg noundef %i)
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void f4(long long i) {}
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// CHECK: define{{.*}} void @f5(i8 inreg noundef signext %a, i16 inreg noundef signext %b)
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void f5(signed char a, short b) {}
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// CHECK: define{{.*}} void @f6(i8 inreg noundef zeroext %a, i16 inreg noundef zeroext %b)
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void f6(unsigned char a, unsigned short b) {}
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enum my_enum {
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ENUM1,
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ENUM2,
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ENUM3,
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};
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// Enums should be treated as the underlying i32.
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// CHECK: define{{.*}} void @f7(i32 inreg noundef %a)
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void f7(enum my_enum a) {}
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enum my_big_enum {
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ENUM4 = 0xFFFFFFFFFFFFFFFF,
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};
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// Big enums should be treated as the underlying i64.
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// CHECK: define{{.*}} void @f8(i64 inreg noundef %a)
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void f8(enum my_big_enum a) {}
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union simple_union {
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int a;
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char b;
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};
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// Unions should be passed inreg.
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// CHECK: define{{.*}} void @f9(i32 inreg %s.coerce)
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void f9(union simple_union s) {}
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typedef struct {
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int b4 : 4;
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int b3 : 3;
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int b8 : 8;
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} bitfield1;
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// Bitfields should be passed inreg.
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// CHECK: define{{.*}} void @f10(i32 inreg %bf1.coerce)
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void f10(bitfield1 bf1) {}
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// CHECK: define{{.*}} inreg { float, float } @cplx1(float inreg noundef %r)
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_Complex float cplx1(float r) {
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return r + 2.0fi;
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}
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// CHECK: define{{.*}} inreg { double, double } @cplx2(double inreg noundef %r)
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_Complex double cplx2(double r) {
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return r + 2.0i;
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}
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// CHECK: define{{.*}} inreg { i32, i32 } @cplx3(i32 inreg noundef %r)
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_Complex int cplx3(int r) {
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return r + 2i;
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}
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// CHECK: define{{.*}} inreg { i64, i64 } @cplx4(i64 inreg noundef %r)
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_Complex long long cplx4(long long r) {
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return r + 2i;
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}
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// CHECK: define{{.*}} inreg { i8, i8 } @cplx6(i8 inreg noundef signext %r)
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_Complex signed char cplx6(signed char r) {
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return r + 2i;
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}
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// CHECK: define{{.*}} inreg { i16, i16 } @cplx7(i16 inreg noundef signext %r)
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_Complex short cplx7(short r) {
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return r + 2i;
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}
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typedef struct {
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int aa; int bb;
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} s8;
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typedef struct {
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int aa; int bb; int cc; int dd;
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} s16;
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// Use 16-byte struct 2 times, gets 8 registers.
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void st2(s16 a, s16 b) {}
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// CHECK: define{{.*}} void @st2(i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %a.coerce2, i32 inreg %a.coerce3, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3)
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// Use 8-byte struct 3 times, gets 8 registers, 1 byval struct argument.
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void st3(s16 a, s16 b, s16 c) {}
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// CHECK: define{{.*}} void @st3(i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %a.coerce2, i32 inreg %a.coerce3, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce)
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// 1 sret + 1 i32 + 2*(i32 coerce) + 4*(i32 coerce) + 1 byval
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s16 st4(int x, s8 a, s16 b, s16 c) { return b; }
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// CHECK: define{{.*}} void @st4(ptr dead_on_unwind noalias writable sret(%struct.s16) align 4 %agg.result, i32 inreg noundef %x, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce)
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// 1 sret + 2*(i32 coerce) + 4*(i32 coerce) + 4*(i32 coerce)
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s16 st5(s8 a, s16 b, s16 c) { return b; }
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// CHECK: define{{.*}} void @st5(ptr dead_on_unwind noalias writable sret(%struct.s16) align 4 %agg.result, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce)
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