7f5d59b38d
The @llvm.amdgcn.cs.chain intrinsic is essentially a call. The call parameters are bundled up into 2 intrinsic arguments, one for those that should go in the SGPRs (the 3rd intrinsic argument), and one for those that should go in the VGPRs (the 4th intrinsic argument). Both will often be some kind of aggregate. Both instruction selection frameworks have some internal representation for intrinsics (G_INTRINSIC[_WITH_SIDE_EFFECTS] for GlobalISel, ISD::INTRINSIC_[VOID|WITH_CHAIN] for DAGISel), but we can't use those because aggregates are dissolved very early on during ISel and we'd lose the inreg information. Therefore, this patch shortcircuits both the IRTranslator and SelectionDAGBuilder to lower this intrinsic as a call from the very start. It tries to use the existing infrastructure as much as possible, by calling into the code for lowering tail calls. This has already gone through a few rounds of review in Phab: Differential Revision: https://reviews.llvm.org/D153761
93 lines
3.7 KiB
C++
93 lines
3.7 KiB
C++
//===- lib/Target/AMDGPU/AMDGPUCallLowering.h - Call lowering -*- C++ -*---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes how to lower LLVM calls to machine code calls.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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namespace llvm {
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class AMDGPUTargetLowering;
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class GCNSubtarget;
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class MachineInstrBuilder;
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class SIMachineFunctionInfo;
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class AMDGPUCallLowering final : public CallLowering {
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void lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
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uint64_t Offset) const;
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void lowerParameter(MachineIRBuilder &B, ArgInfo &AI, uint64_t Offset,
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Align Alignment) const;
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bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
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SmallVectorImpl<BaseArgInfo> &Outs,
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bool IsVarArg) const override;
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bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
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ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
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public:
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AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
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bool lowerReturn(MachineIRBuilder &B, const Value *Val,
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ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI) const override;
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bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs) const;
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bool lowerFormalArguments(MachineIRBuilder &B, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const override;
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bool passSpecialInputs(MachineIRBuilder &MIRBuilder,
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CCState &CCInfo,
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SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
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CallLoweringInfo &Info) const;
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bool
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doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info,
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MachineFunction &MF,
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SmallVectorImpl<ArgInfo> &InArgs) const;
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bool
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areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF,
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SmallVectorImpl<ArgInfo> &OutArgs) const;
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/// Returns true if the call can be lowered as a tail call.
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bool
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isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info,
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SmallVectorImpl<ArgInfo> &InArgs,
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SmallVectorImpl<ArgInfo> &OutArgs) const;
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void handleImplicitCallArguments(
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MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst,
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const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI,
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CallingConv::ID CalleeCC,
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ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const;
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bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
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SmallVectorImpl<ArgInfo> &OutArgs) const;
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bool lowerChainCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const;
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bool lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const override;
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static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
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static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
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};
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} // End of namespace llvm;
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#endif
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