fef54d0393
New register bank select for AMDGPU will be split in two passes: - AMDGPURegBankSelect: select banks based on machine uniformity analysis - AMDGPURegBankLegalize: lower instructions that can't be inst-selected with register banks assigned by AMDGPURegBankSelect. AMDGPURegBankLegalize is similar to legalizer but with context of uniformity analysis. Does not change already assigned banks. Main goal of AMDGPURegBankLegalize is to provide high level table-like overview of how to lower generic instructions based on available target features and uniformity info (uniform vs divergent). See RegBankLegalizeRules. Summary of new features: At the moment register bank select assigns register bank to output register using simple algorithm: - one of the inputs is vgpr output is vgpr - all inputs are sgpr output is sgpr. When function does not contain divergent control flow propagating register banks like this works. In general, first point is still correct but second is not when function contains divergent control flow. Examples: - Phi with uniform inputs that go through divergent branch - Instruction with temporal divergent use. To fix this AMDGPURegBankSelect will use machine uniformity analysis to assign vgpr to each divergent and sgpr to each uniform instruction. But some instructions are only available on VALU (for example floating point instructions before gfx1150) and we need to assign vgpr to them. Since we are no longer propagating register banks we need to ensure that uniform instructions get their inputs in sgpr in some way. In AMDGPURegBankLegalize uniform instructions that are only available on VALU will be reassigned to vgpr on all operands and read-any-lane vgpr output to original sgpr output.
75 lines
2.4 KiB
C++
75 lines
2.4 KiB
C++
//===-- AMDGPURegBankSelect.cpp -------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// Assign register banks to all register operands of G_ instructions using
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/// machine uniformity analysis.
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/// Sgpr - uniform values and some lane masks
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/// Vgpr - divergent, non S1, values
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/// Vcc - divergent S1 values(lane masks)
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/// However in some cases G_ instructions with this register bank assignment
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/// can't be inst-selected. This is solved in AMDGPURegBankLegalize.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/InitializePasses.h"
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#define DEBUG_TYPE "amdgpu-regbankselect"
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using namespace llvm;
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namespace {
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class AMDGPURegBankSelect : public MachineFunctionPass {
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public:
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static char ID;
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AMDGPURegBankSelect() : MachineFunctionPass(ID) {
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initializeAMDGPURegBankSelectPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "AMDGPU Register Bank Select";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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// This pass assigns register banks to all virtual registers, and we maintain
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// this property in subsequent passes
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MachineFunctionProperties getSetProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::RegBankSelected);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, DEBUG_TYPE,
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"AMDGPU Register Bank Select", false, false)
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INITIALIZE_PASS_END(AMDGPURegBankSelect, DEBUG_TYPE,
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"AMDGPU Register Bank Select", false, false)
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char AMDGPURegBankSelect::ID = 0;
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char &llvm::AMDGPURegBankSelectID = AMDGPURegBankSelect::ID;
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FunctionPass *llvm::createAMDGPURegBankSelectPass() {
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return new AMDGPURegBankSelect();
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}
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bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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return true;
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}
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