21f7c62627
This patch adds latency mutations as a scheduling related speedup for the above mentioned cores. When benchmarking this pass on selected benchmarks we see a performance improvement of 1% on most benchmarks with some improving by up to 6%. Author: David Penry <david.penry@arm.com> Co-authored-by: Nashe Mncube <nashe.mncube@arm.com
57 lines
1.8 KiB
C++
57 lines
1.8 KiB
C++
//===- ARMLatencyMutations.h - ARM Latency Mutations ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the ARM definition DAG scheduling mutations which
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/// change inter-instruction latencies
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_LATENCYMUTATIONS_H
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#define LLVM_LIB_TARGET_ARM_LATENCYMUTATIONS_H
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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namespace llvm {
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class AAResults;
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class ARMBaseInstrInfo;
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/// Post-process the DAG to create cluster edges between instrs that may
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/// be fused by the processor into a single operation.
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class ARMOverrideBypasses : public ScheduleDAGMutation {
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public:
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ARMOverrideBypasses(const ARMBaseInstrInfo *t, AAResults *a)
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: ScheduleDAGMutation(), TII(t), AA(a) {}
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void apply(ScheduleDAGInstrs *DAGInstrs) override;
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private:
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virtual void modifyBypasses(SUnit &) = 0;
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protected:
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const ARMBaseInstrInfo *TII;
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AAResults *AA;
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ScheduleDAGInstrs *DAG = nullptr;
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static void setBidirLatencies(SUnit &SrcSU, SDep &SrcDep, unsigned latency);
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static bool zeroOutputDependences(SUnit &ISU, SDep &Dep);
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unsigned makeBundleAssumptions(SUnit &ISU, SDep &Dep);
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bool memoryRAWHazard(SUnit &ISU, SDep &Dep, unsigned latency);
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};
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/// Note that you have to add:
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/// DAG.addMutation(createARMLatencyMutation(ST, AA));
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/// to ARMPassConfig::createMachineScheduler() to have an effect.
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std::unique_ptr<ScheduleDAGMutation>
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createARMLatencyMutations(const class ARMSubtarget &, AAResults *AA);
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} // namespace llvm
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#endif
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